In this post I am writing some generally asked questions for DFT profile.
Q1. What is Fault Coverage?
Q2. What is test
coverage?
Q3. What is Design For Test (DFT)?
Q4. What is the difference between sequential and combinational atpg?
Q5. What is Stuck-at Fault Models?
Q6. What is Scan design?
Q7. What is Stuck-at 0 and 1 fault?
Q8. What is BIST?
Q9. What is LBIST?
Q10. What is MBIST?
Q11. When are DFT and Formal verification used?
Q12. What is Controllability
and observability?
Q13. What are scan chains?
Q14. How normal flop is transformed
into a scan flop?
Q15. What is the
difference between normal flip flops and scan flip flops?
Q16. Determine the test vector
generated by ATPG to detect a stuck-at-0 (S-a-0) fault at the
net‘d’
in the given circuit.
 |
| Figure 1 |
Q17. How many
stuck at faults can be detected in 2 input AND gate?
Q18. If we
have the stuck at 0 at output (F) as shown below. If we have the stuck at 0 at
F what are the patterns can detect the stuck at 0?
 |
| Figure 2 |
Q19. What are the difference between Test Coverage and
Fault Coverage?
Q20. What do we mean by fault simulation in DFT terminology?
Click here for part 2
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