Floorplanning

What is Floorplanning?

• Floorplanning is the most important process in Physical Design. Floorplanning is the process of placing blocks/macros in the chip/core area.In this step we have netlist which describes the design and the various blocks of the design and the interconnection between the different blocks. The netlist is the logical description of the ASIC design. Floorplan is the physical description of the ASIC design. In floorplanning we are mapping the logical description of the design to the physical description.
• In this step, we define the size of chip/block, allocates power routing resources, place the hard macros, and reserve space for standard cells.
• It also determines the I/O pin or pad placement.
• A good floorplan can be make placement, CTS, routing and timing closure easy.
• A bad floorplan can affects the area and power and reliability of chip.

Initial Floorplan

Objectives Of Floorplanning

• Minimize the area.
• Minimize the timing.
• Reduce the wire length
• Making routing easy.
• Reduce the IR drop.

Inputs for Floorplanning

• Gate level netlist (.v)
• Physical and logical libraries.
• Synopsys design constraints(.sdc).
• TLU+ files.
• Technology files(.tf).
• Physical partitioning information of the design. 
• Floorplanning parameters like height, width, aspect ratio etc.

Output of Floorplanning

• Die/Core area
• I/O pad information
• Placed macros information
• Standard cell placement areas
• Power grid design
• Blockages are defined

Floorplanning Steps

• Define width and height of core and die.
• I/O pad placement
• Macros placement
• Create standard cell row for standard cell placement
• Power planning
• Logic cell placement blockage

Floorplan Steps

Define Width and Height

   

I/O Pin  Placement

Power Planning

Types of floorplan Techniques

• Abutted floorplan: Channel less placement of blocks.
• Non-abutted floorplan: Channel based placement of blocks.
• Mix of both: Partially abutted with some channels.

Floorplan Control Parameters

• Aspect Ratio: Aspect ratio is defined as the ratio of height to width of the chip.Aspect ratio defined the size and shape of the chip.If AR =1 shape of chip will be square.If AR is other than 1 it signify the rectangular shape.AR=Height/Width.The aspect ratio effects the routing resources available in the design.It effects the congestion.

• Core Utilization: Core Utilization defines the area occupied by standard cell, macros and blockages.
• Core Utilization=(standard cell area+ macro cells area+pad area)/ total core area.
• If core utilization of 0.8 means that 80% of the area is available for placement of cells, whereas 20% is left for routing.

IO/Pin placement

• IO/ Pins are placed at the boundary of the chip.Pin Placement is an important step in floorplanning. The placement of  I/O pads depends on packaging also.Pin placement can be done based on timing, congestion and utilization of the chip.To place IO pads we use a script to place them.If we are doing a digital block, we will need to place pins around the boundary to connect to the higher level routing.

Macro placement

• The placement of macros takes place after I/O placement. Macros may be memory block, analog blocks. Macro placement can be manual or automatic. Manual macro placement is more efficient when there are few macros to be placed. Automatic macro placement is more appropriate if number of macros is large.
• Depending on how the macros are placed, the tool places the standard cells in the core.
• All macros should be placed at the boundary.
• Spacing between macros should be enough for routing & power grid.
• Check the orientation and pin directions of all macros.

Types of macros

• Hard macros: Hard macro is a block that is generated in a methodology other than place and route and is imported into GDSII file.Hard macros are block level designs which are optimized for power, area and timing.While accomplishing physical design it is possible to only access pins of  hard macros.
• Soft macros: Soft macros are synthesizble RTL form.Soft macros are editable and can contain standard cell and other soft macros.Soft macros carry greater IP protection risks because RTL source code is more portable.

Macro placement Guidelines

• Use flylines and make sure you place blocks that connects to each other closer.
• If hard macros connect to IO, place them near the respective IO.
• Spacing between two macros.
• Provide a halo space around all sides of the macros.
• Keep placement blockages at the corners of macros.
• Left space between macros and block boundary to allow buffers/inverter to be inserted  and power rails.
• Macros that are communicating with pins/ports of core place them near to core boundary.
• Consider the power straps while placing macros.
• Avoid crisscross connection of macro placement to save the routing resources, congestion and other issues related to timing and placement of standard cells.
• Avoids notches while placing macros.

Channel spacing between macros=(No. of pins x pitch)/number of layers either horizontal or  vertical

Flylines

• Macros are placed manually using flylines.
• Flylines are virtual connection between macros and macros to IO pads.
• Flylines helps designer to reduce the routing resources.
• Flylines are of two types:
• Macros to IO pin flylines
• Macros to Macros flylines

Blockages 

• Blockages are specific location where placing of cells are blocked.
• Blockages acts like guidelines for placement of standard cells.
• Blockages will not be guiding the tool to place the standard cells at some particular area, but it won’t allow the tool to place the standard cell in the blocked areas.

Types of Blockages

• Hard Blockages: Blocks all standard cells and  buffers to be placed.Use to Avoid routing congestion at macro corners.Control power rails generation at the macros.
• Soft Blockages: Soft blockages allows only buffers can be placed and standard cells cannot be placed.
• Partial blockages:By default a placement blockage has a blockage factor of 100%.So no cells can be placed in that area but if we want to reduce placement density without blocking 100% area we can change the blockage factor.

Placement blockages

• Define Standard cell and macros area
• Reserve channels for buffer insertion
• Prevent congestion near macros
• Prevent cells from being placed at or near macros.

Keepout Margin(HALO)

• Halo is the region around the fixed macros in the design so that no other macros and standard cell can be placed near to macros boundary.
• Halo allows placement of buffers and inverters in its area.
• Halos of adjacent macros can overlap.
• If the macros are moved from one place to another place , halos will also be moved.

How to qualify a Floorplan?

• All the macros should be placed at the boundary.
• Proper channel spacing is there between macros.
• Check Power grid connections to all the macros and preplaced cells.
• Remove all unnecessary placement blockages & routing blockages.
• Check power mesh in different voltage area.

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vlsi4freshers

Hi I’m Designer of this blog.