**1. Complete the blanks in the following question with the appropriate answer.**

Given Base CPI(Cycles per instruction) = 1, clock frequency = F GHz, Miss rate for L2 cache =M%, access time of L2 cache = A ns Miss rate for L3=N%, access time for L3 cache=B ns

Main memory access time = C ns

We have two memory system:

System 1- with L3 cache only

System ___________will have higher performance gain.(1 for system 1 and 2 for system 2).

The performance ratio of the high performance system to the lower performance system (round off integer part) is __________.

**2. Complete the blanks in the following question with the appropriate answer.**

A system has X MB, Y way set associative cache with block size Z Bytes. Processor generates M bit addresses in addition to tag there are 2 valid bit, 1 replacement bit and 1 modified bit.

The size of the tag array is _________ KBytes.

**3. Complete the blanks in the following question with the appropriate answer.**

Consider the following circuit of identical NMOS transistors connected as shown in the figure below. VDD=5V; VTH (transistor threshold voltage) = 2V, Vin = 4V.

a. Voltage at node N1 is ______V.

b. Voltage at node N2 is ______V.

c. Voltage at node N3 is ______V.

**4. Complete the blanks in the following question with the appropriate answer.**

In a digital design, power gating is implemented for standard cells with efficiency of 80% and power gating is implemented for RAMs with efficiency of 90%.

Standard cell dynamic power = 300mW and RAMS Dynamic power = 150mW.

Standard cell leakage power = 100mW and RAMS Leakage Power = 50mW.

10% of the standard cells are always ON and not power gated.

When the design is power-gated, the dynamic power is _______ mW and leakage power is ________ mW.

**5. Complete the blanks in the following question with the appropriate answer.**

The following circuit consists of two identical flops F1, F2, a combinational logic cloud, and 10 identical clock buffers. The relevant timing parameters are listed in the table below. The circuit has a maximum operating frequency of 500 MHZ.

Setup time of flop = 0.2ns

Hold time of flop = 0.0ns

Tclk-q of flop = 0.2ns

Based on the above data ,TPD = ___________ ns.

**6. Complete the blanks in the following question with the appropriate answer.**

If the signal nets "Y1" and "Y2" are routed on adjacent tracks, a crosstalk event might occur on these nets in the window ________ ps to _______ ps.

**7. Complete the blanks in the following question with the appropriate answer.**

Two flip flops are placed far from each other with no combinational logic in between. The distance between the two flop is 60mm, data wire delay is 400ps/mm and clock wire delay is 200ps/mm. Setup time of the flops is 0.5ns and clock to q delay is 0.5 ns. The clock period is 5ns. We need to insert retiming flops in the data path to meet timing constraints

Assuming clock and data are traveling together in the same direction. Setup time and clock to Q delay of retiming flops is same as above flops.

The minimum number of retiming flops required for above circuit to work as per given timing constraints is __________.

**8. Complete the blanks in the following question with the appropriate answer.**

Design operating point changes from <frequency f, Voltage 2V> to <frequency 4f, voltage 3V).

Dynamic power is multiplied by a factor of (enter number): _________.

**9. Complete the blanks in the following question with the appropriate answer.**

Consider an interface between two modules, Module A & Module B, operating at frequencies fA & fB respectively.

Choose the right FIFO depth required between the two modules so that there is no underflow or overflow, based on the below parameters Module A is writing data into Module B.

FIFO depth = _________.

**10. Complete the blanks in the following question with the appropriate answer.**

In the given circuit Clk is running at frequency F1. Input A is square wave with frequency F2.

Counter increments by 1 only when input "Incr" is 1.

**11. Complete the blanks in the following question with the appropriate answer**

what will be the output frequency for the given input frequency "Fin". Set and clear are always tied off to zero.

Input Frequency (Fin) KHz =25

Output Frequency (KHz) ____________.

**12. Complete the blanks in the following question with the appropriate answer.**

The gates have below (rise, fall) delay numbers.

For t>0 output Z=0 for a duration of ________ ns.

**13. Complete the blanks in the following question with the appropriate answer.**

A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN.

In each cycle, GREEN is turned on for "G" seconds, YELLOW is turned on for "Y" seconds and the RED is turned on for "R" seconds. (FSM).

This traffic light has to be implemented using a finite state machine The only input to this FSM is a clock of "N" seconds period.

Green "G" (in seconds)=12

Yellow "Y" (in seconds)=3

Red "R" (in seconds)=15

Clock Period N (in seconds)=3

The minimum number of flip flops required to implement this logic_________.

**14. Complete the blanks in the following question with the appropriate answer.**

A digital logic is implemented in the fashion shown in the diagram.

Inputs of the first xor gate are : (1, X).

All the Xor-gates after this stage have inputs as : (output of previous stage, X).

"N" Xor-gates are connected in series as per the diagram.

Number of Xor gates connected in series (N)= 50

1) Output of Nth xor-gate is ____________.

2) Output of "N+1" xor-gate when passed through a not-gate is __________.

Note: If the answer is NOT(x) or inversion of x then mention it as either x' or x 'or xbar.

**15. Complete the blanks in the following question with the appropriate answer.**

Consider a rotating disk, with 1/4th of the disk painted black and white alternatively.

There are two sensors A and B mounted close to the disk, but not touching the disk. Sensors A and B are 45 degrees apart as shown.

The sensors output logic 1 when the color of the disk below it shall be white and logic 0 when it shall be black For eg: In the current position both the sensors output logic 1.

What shall be the maximum rotations per micro-second possible for the disk, for the output Q2 to toggle and no set-up violation to occur at FF2.

__________

Note With + indicating rotation in clockwise direction while - indicates in anticlockwise. For eg if your answer is 100 rotations per microsecond in clockwise direction answer as +100.

**16. Complete the blanks in the following question with the appropriate answer.**

M takes X no. of days to complete one-fifth of the work, N takes Y no. of days to complete one-tenth of the same work and O takes Z no. of days to complete half the work.

If all of them work together for 4 days and M and O quit, how long will it take for N to complete the remaining work done.

N will complete the work in _______ days.

Note: Round the number to nearest Integer. For Ex: if the answer is 25.1 then enter 25, if the answer is 25.9 then enter 26.

**17. Complete the blanks in the following question with the appropriate answer.**

A man can row A kmph in still water. If the river is flowing at a speed of B kmph, it takes him C minutes to row to a place and back. How far is the place?

Note: Pls truncate to 2 decimal values.

For example:

if the answer is 3.452, enter 3.45

if the answer is 5, enter 5.00

If the answer is 5.5, enter 5.50

Place is _________ Km away.

**18. Complete the blanks in the following question with the appropriate answer.**

How many zeroes are there at the end (Isb side), in the decimal expansion of 2021! (2021 factorial)?

The number of zeroes is:____________.

**19. Complete the blanks in the following question with the appropriate answer**

Eight ants are present, one at each vertex of an octagon. Each ant randomly picks a direction and starts to move along the edge of the octagon.

The probability that none of the ants collide is 1/________.

**20. Complete the blanks in the following question with the appropriate answer.**

What is the output of the following program?

#include<stdio.h>

main()

{

int i, j; // Assume the following values for i & j

printf("%d %d", i<<j,i >>j);

}

Values:

i=8

j=2

1) First Output ______.

2) Second Output ______.

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