UVM Interview Questions Part 2

1. In UVM, which of the following classes are continually created and destroyed during simulation? a) Transactions classes b) Componen...

System Verilog Interview Questions Part 3

1.Code coverage is specification coverage, while functional coverage is implementation coverage. a) TRUE b) FALSE 2. Which of the fo...

Basics Of UVM:Testbench Architecture

Universal Verification Methodology (UVM) is a system verilog language based verification methodology which is widely used across VLSI indu...

Computer Architecture Interview Questions Part 2

1. Compared to RISC processors, CISC processors contain a) More registers and smaller instruction set b) Larger instruction set and le...

Computer Architecture Interview Questions Part 1

1.What is pipelining? 2.For a pipeline with 'n' stages, what’s the ideal throughput? What prevents us from  achieving this ideal...

System Verilog Interview Questions Part 2

1.What is default value of logic data type? a)x b)0 c)1 d)z 2.Which of the following data types is not 2 state data types? a)i...