Power Planning

Power Planning Basics

• Power planning is stage typically part of the floorplanning stage , in which power grid network is created to distribute the power uniformly to each part of the chip.
• Power planning means to provide power to the every macros and standard cells and all others cells are present in the design.
• Power planning is also called Pre-routing as the Power Network Synthesis (PNS) is done before actual signal routing and clock routing.
• Power ring is designed around the core.
• Power rings contains both VDD and VSS rings.After the ring is placed a power is designed such that power reaches all the cells easily, power mesh is nothing but horizontal and vertical lines on the chip.
• During power planning, the VDD and VSS rails also have to be defined.
• Objective of power planning is to meet IR drop budget.
• Power planning involves- calculating number of power pins required,number of rings and straps,width of rings and straps and IR drop.

Overview of Power Planning

Inputs for power planning

• Floorplan database.
• Power rings and power straps width.
• Power budget.
• Spacing between the VDD and VSS straps.

Output of power planning

• Design with power structure.
• Floorplan with synthesized power mesh.

There are three level of power distribution

• Power Rings: Carries VDD and VSs around the chip.
• Power Straps: Carries VDD and VSS from rings across the chip.
• Power Rails: Connect VDD and VSS to the standard cells.

There are two types of power planning and management

Core Cell Power Management

• Power rings are formed around the core.
• Straps and trunks are created for macros according to power requirement.
• The horizontal and vertical layers are connected each other using proper via cut.

I/O Cell Power Management

• Power rings are formed for I/O cells.
• Trunks are created between core power ring and power pads.

Steps to create PG mesh

• Establish Logical PG Connectivity
• Create core rings
• Create Straps
• Preroute Cells
• Verify PG net connectivity

Power Planning Calculations

• Total number of core power pad’s required.
• Core Current=(Core Power)/(Core Voltage ).
• Total power P(total) = P(dynamic )+ P(static).
• No.Of Power Pads.
• No.Of Power Pins.
• Core PG Ring Width.

IR Drop Analysis

• The power supply in the chip is distributed uniformly through metal layers Vdd and Vss across the design. These metal layers have finite amount of resistance.
• When voltage is applied to this metal wires current starts flowing through the metal layers and there is some voltage drop due to resistance of metal wires and current. This drop is called IR drop.
• Voltage drop in supply voltage,the delays are increased,this may lead to setup time and hold time violations.

IR drops are of two types

• Static IR drop: Static IR drop is the drop, when a constant current draws through the power network with varying resistance,this IR drop occurs when the circuit is in steady state.
• Methods to Improve static IR drop
• Increase the width of wire
• Increase number of wire
• Dynamic IR drop: Dynamic IR drop is the drop when the high current draws the power network due to the high switching of the cell.
• Methods to Improve Dynamic IR drop
• Place decap cell near high switching cells.
• Increase the number of straps.

Method to reduce the voltage IR drop

• Reducing the wire resistance.
• Increase the number of Vdd and Vss pads in the chip to reduce the current consumption for each pair of Vdd and Vss pads.
• Reducing the current consumption (Iavg) of logic gates.

Sanity checks after power planning

• All the cells should get a power.
• Fix if any PG open/shorts exists in the design.
• Power DRC’s.
• Understand the IR drop impact for design PG grid and improve the grid to provide acceptable IR drop.

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vlsi4freshers

Hi I’m Designer of this blog.