In this post I am writing some frequently asked Physical Design Interview Questions
Q8. What is IR Drop?
Q1. What are the inputs files for
Physical Design Flow?
- Logical libraries (.lib format) provided by vendor
- Physical libraries (.lef format) provided by vendor
- Technology libraries (.tf(synopsys) format) provided by fabrication Team
- TLU+ file (.tlup format) provided by fabrication Team
- Netlist (.v format) provided by Synthesis Team
- Constraints files (.sdc format) provided by Synthesis Team
- DRC(Design Rule Check)
- LVS (Layout vs schematic)
- ERC (Electrical rule check)
- Antenna Check
- If the number of routing tracks available for routing is less than the required tracks then it is called congestion.
- Clock gating
- Reduce supply voltage
- Reduce switching activity
- Use multiple voltage domains –multi vdd.
- Switching of the signal in one net (aggressor) can interfere neighbouring net (victim)due to cross coupling capacitance this is called cross talk. Cross talk may lead to setup and hold violation.
- By checking the total area of the design.
- Signal integrity is the ability of an electrical signal to carry information reliably and resist the effects of high-frequency electromagnetic interference from nearby signals.
- IR drop, cross talk, electro migration, ground bounce are signal integrity issues.
- Crosstalk may lead to set up and hold violation.
- If IR drop is more delay is increases.
- The power supply in the chip is distributed uniformly through metal layers Vdd and Vssacross the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and there is some voltage drop due to resistance of metal wires and current. This drop is called IR drop.
- During the fabrication of MOS integrated circuits, especially at the time of plasma etching, there will be a chance of collecting more charges at the gate and causes damage to the gate oxide layer since it is very thin. This condition is known as Antenna effect.
- Check legalization for any overlapping.
- Check global congestion and pin density.
- Check cell density.
- Check whether all don't touch cells and nets are preserved.
- Check for setup time violation
- Normal buffers have unequal rise and fall time.
- Clock buffers have equal rise and fall time.
- Clock Tree Synthesis (CTS) is a process which makes sure that the clock gets distributed evenly to all sequential elements in a design.
- CTS is the process of insertion of buffers or inverters along the clock paths of design in order to achieve minimum skew or balanced skew.
- Die/Block area
- I/O pad/placed
- Macro placed
- Power grid design
- Power pre-routing
- Standard cell placement areas
- Double spacing
- Buffer insertion
- Shielding
- Slack is the difference between the required time and the arrival time of a signal.
- Setup slack = Required time - Arrival time
- Hold slack = Arrival time - Required time
Q16.
Define Clock latency.
- Clock latency is defined as the amount of time taken by the clock signal in travelling from its source to the sinks or destination.
- Routing is nothing but connecting the various blocks in the chip with one another. This includes the interconnection of the standard cells, the macro pins, the pins of the block boundary.
- Global Routing
- Track Assignment
- Detailed Routing
- Search and repair
Click here for more detail about routing
Click here for part 2
https://www.vlsi4freshers.com/2020/07/physical-design-interview-questions-part2.html
Click here for part 2
https://www.vlsi4freshers.com/2020/07/physical-design-interview-questions-part2.html
good questions and explanation
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