In this post I am writing some frequently asked STA Interview Questions
Q1. What is wire load
model?
Q2. What does SDC
constraints has?
Q3. Hold time does
not depend on clock. Is it true? If so why?
Q4. What are the
various timing-paths which should be taken care in STA?
Q5. What is the
difference between local-skew, global-skew and useful-skew?
Q6. What is clock
skew?
Q7. What are
multi-cycle paths?
Q8. What is false
path? Explain with example.
Q9. What is asynchronous
and clock gating timing path? Explain with example.
Q10. What factors
decides the setup time of flip-flop?
Q11. How can you
avoid cross talk?
Q12. In which case
inserting a buffer will solve the setup timing?
Q13. What is slack?
Q14. How do you fix
Noise violation?
Q15. What is cloning
and buffering?
Q16. What is Arrival
time and Required Time?
Q17. What is timing
analysis? Why it’s so important these days?
Q18. Explain time
borrowing with example.
Q19. How to calculate
setup and hold time violation in a design?
Q20. What are delay
models and difference between them?
Q21. How delay varies
with different PVT conditions? Explain
with the help of graph.
Q22. In which factor Delay
of a cell depends.
Q23. What do you mean
by the de-rating value?
Q24. What is virtual clock?
Q25. We got some timing violation when
I reduced the frequency by 1/10th then circuit is working enormous. What
violation is occurred?
1) Setup 2) Hold 3) Both
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