In this post I am writing some frequently asked Digital Design Interview Questions

Q1. The minimum number of flip-flops that can be used
to construct a mod-5 counter is.

- 3 flip flop are required.

Q2.
Design an inverter and buffer using
a XOR gate.

Q3. Design a 4:1 MUX using 2:1 multiplexers?

Q4. What is the difference between a flip-flop and a
latch?

- Latch continuously check its inputs and changes its output correspondingly. Latches are level sensitive. Latches based on enable signal.
- Flip flop continuously check its inputs and changes its output correspondingly only at times determined by clocking signal. Flip flop are edge sensitive. Flip flop based on clock signal.

Q6. Convert a JK flip-flop to D
Flip-flop.

Q7.

**Difference between a synchronous counter and an asynchronous counter?**- In synchronous counters, the clock inputs of all flip-flops are connected to a common Clock signal and hence all flip-flops changes synchronously. Synchronous are faster. Synchronous counters also called ring counter.
- In asynchronous counters, the clock input is connected only to the first flip-flop and the Output for first flip-flop is connected to the clock input of second flip-flop and similarly every other flip-flop is clocked by the output of previous flip-flop. Asynchronous counters also called ripple counter. Asynchronous are slower.

Q9. What is the difference between a Moore and a Mealy
finite state Machine?

- A Moore Machine is a finite state machine whose output depends only on the present state.
- A Mealy Machine is a finite state machine whose output depends on the present state as well as the present input.

Q11. What is transparent latch?

- D-Latch is called transparent Latch. It transfers the data as it is to the output on enable.

Q13. What is race-around
condition?

Q14. Draw the circuit for a D
flip flop with Synchronous Reset?

Q15. Design a 4-bit binary
counter using TFFs?

Q16. How many unused states will
be there in a Johnson’s counter with N flip-flops?

- For N-flops, the total possible states = 2^N.
- The number of states of a Johnson counter = 2N
- The number of unused states = 2^N – 2N.

- (a) 4x10= 40ns
- (b) 10ns

- Binary number is 10001.

Q20. Design half subtractor using
NOR gates. (Cadence 2019)

Q21. Implement a full adder using
two 4:1 Muxes?

Q22. . Design a frequency divide-by-2
circuit using D flip flop and external gates which gives (a) 50% duty cycle (b) 25%
duty cycle?

Q23. What is the output frequency
of a 4-bit binary counter for an input clock of 160 MHz.

- The output of last flip flop of a 4-bit counter is equal to the input clock/16.
- So output frequency = 160MHz/16 = 10MHz.

Q25. The
gate delay of an NMOS inverter is dominated by charge time rather than
discharge time because.

- The load transistor has smaller W/L ratio as compared to driver transistor.

**Click here for part 2**

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