1. With a multiple fault model with k types of faults, a circuit with n fault sites will have number of faults equal to.
a) (k+1)^n
b) (k+1)^n-1
c) (k)^n
d) (k)^n-1
2. Three modes of operation in scan are.
a) Normal, Scan, Capture
b) Scan, Shift, Capture
c) Normal, Shift, Capture
d) None of the above
3. Inputs to a scan cell are
a) Data and Scan
b) Serial and Scan
c) Parallel and Serial
d) Parallel and Scan
4. Number of clocks in a clocked scan cell is.
a) 1
b) 2
c) 4
d) None of the above
5. Muxed-D scan cell has
a) multiplexer and a latch
b) multiplexer or a latch
c) multiplexer or a flipflop
d) multiplexer and a flipflop
6. Sequential depth of a structure graph is equal to its maximum.
a) Nodes
b) Level
c) Degree
d) None of the above
7. Asynchronous set/reset is.
a) Avoided for testing
b) May be used for design
c) Both a and b
d) None of the above
8. Fault simulation detects.
a) Fault coverage
b) Faulty outputs
c) Set of undetected faults
d) All of the above
9. For sequential circuits, which of the fault simulation is the most popular?
a) Differential fault simulation
b) Concurrent fault simulation
c) Both a and b
d) None of the above
10. ATPG stands for
a) Automatic Test Pattern Generator
b) Active Test Pattern Generator
c) Advanced Test Pattern Generator
d) None of the above
11. Find the test vector generated by ATPG to detect a stuck-at-0 fault at the net ‘d’ in the given circuit.
a) a = 1, b = 1, c = 0
b) a = 1, b = 1, c = 1
c) a = 0, b = 1, c = 0
d) a = 0, b = 1, c = 1
12.The total number of test patterns required to exhaustively test a 128-to-1 multiplexer with minimum number of select lines is.
a) 2^135
b) 2^128
c) 2^256
d) None of the above
13. Apply D-algorithm, find the test vector to propagate a stuck-at-1 fault at net ‘v’ in the circuit given below.
a) x = 0, y = 0, w = 1, z = 0
b) x = 0, y = 1, w = 1, z = 0
c) x = 0, y = 0, w = 0, z = 0
d) Any of the above
14. Apply PODEM algorithm, find which of the following faults become untestable for the circuit given below.
a) Stuck-at-1 at g
b) Stuck-at-0 at i
c) Stuck-at-1 at h
d) Stuck-at-1 at i
15. Which of the following faults for the given circuit are undetectable when y = 0?
a) f stuck-at-1
b) u stuck-at-1
c) v stuck-at-1
d) y stuck-at-1
16. One-hot decoder is used in BIST to avoid bus contentions arising due to.
a) Tri-state Buses
b) Floating Ports
c) Multi-Cycle Paths
d) False Paths
17. For LFSR tuning in BIST, the parameters that can be controlled are
a) Polynomial and Seed value
b) Polynomial and Size
c) Size and Speed
d) None of the above
18. What is the advantage of clock gating?
a) It helps to reduce the number of test pattern to test a circuit
b) It helps to reduce the test mode power
c) It improves the fault coverage
d) None of the above
19. For a 4-bit ripple carry adder with all full adders, the probability of detecting a stuck at- 1 fault at one of its output bits, given the test set contains 50 test vectors is
a) 50/512
b) 50/256
c) 206/256
d) None of the above
20. Input to a testing process.
a) Circuit under test(CUT)
b) Test stimuli
c) Both a and b
d) None of the above
Answers: 1.b 2. c 3.a 4.b 5.d 6.b 7.c 8.d 9.c 10.a 11.b 12.a 13.d 14.d 15.c 16.c 17.a 18.b 19.a 20.c
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