Routing Basics
  • Routing is the stage after CTS,routing is nothing but connecting the various blocks in the chip with one an other.
  • Routing creates physical connections to all clock and the signal pins through metal interconnects.
  • After CTS, we have information about the exact location of placed cells, blockages, clock tree buffers/inverters and I/O pins. The tool depends on this information to electrically complete all connections.
  • In routing stage, metal and vias are used to create the electrical connection in layout, to complete all connections defined by the netlist.
Goals of Routing
  • Minimize the total wire length
  • Meeting the timing DRC's
  • Minimize the number via's
  • No Design Rules Check(DRC) violations
  • No LVS errors
  • Minimum routing area.
  • Minimizing the congestion hotspots
Inputs for routing
  • Technology file
  • TLU+ file
  • SDC file
  • Design with complete CTS
Output of routing
  • Design with completed interconnection and geometric layout of the nets
Checklist before routing
  • Placement and CTS and optimization should be completed
  • PG nets should be pre-routed
  • Timing DRC and QoR post CTS should be acceptable
  • High fanout nets(HFNS) should not be greater than the specified limit
  • Check for blocked PG ports
  • Checks for overlapping cells in the design
  • Estimated congestion –acceptable
  • Check routability
Routing Constraints
  • Constraining the routing density
  • Constraining the off-grid routing
  • Block the routing in the specific regions
  • Design Rule constraints
  • Performance constraints
Design rule constraints
Stages of Routing
  • Global routing
  • Track assignment
  • Detailed routing
  • Search and repair
Global routing
  • Define the routing regions.
  • It generate a tentative route for each net.
  • Each net is assigned to set of routing regions.Routing regions are those so which interconnecting wires are laid out.
  • Partition the routing area into tiles/rectangles called global routing cells or gcells.
  • Global routing assigns nets to specific gcells but it does not define the specific tracks for each of them.
  • By default the width of the gcells is same as the height of a standard cell and is aligned with the standard cell rows.
  • Each gcell has a finite number of horizontal and vertical tracks.
  • It does not specify the actual layout of wires.
  • Objective of global routing -minimize total wire length,minimize total overflow.
Global Routing
Track assignment
  • Track assignment is a stage where the routing tracks are assigned for each global routes.
  • The tracks are assigned in vertical and horizontal direction.
  • The number of routing layers that are available depend on the design and also, if the die size is more, the greater the routing tracks.
  • Track Assignment replaces all global routes with actual metal layers.
  • There will be many DRC, Signal integrity and timing related violations.
Detailed Routing
  • In this stage the actual connection between all the nets takes place. It creates the actual via and metal connections.
  • It specifies the specific tracks for the interconnection, each layer has its own routing grid, rules.
  • The violations that were created during the track assignment stage are fixed in this stage.
  • The main goal of detailed routing is to complete all of the required interconnect without leaving open,shorts or spacing violations.
  • The detailed routing starts with the router dividing the block into specific areas called switch boxes or Sbox, which are generally expressed in terms of gcells.
  • These boxes are align with the gcell boundary.
  • Objective of detailed routing is to minimize the total area, wire length and meet timing constraints.
  • The actual layout of wires is specified.
Detail Routing
Types of Detail Routing
  • Grid based routing
  • Grid less routing
Grid Based Routing
  • A grid is super imposed on the routing region.
  • Wires follow paths along the grid lines.
Grid Based Routing
Grid Less Routing
  • Does not follow the gridded approach.
  • It is generally much slower than grid based routing.
Grid Less Routing
Search and Repair
  • It is performed during detailed routing after the first iteration.
  • In search and repair, shorts and spacing violations are fixed.
Checklist after routing
  • Acceptable congestion
  • Acceptable DRV’s.
  • Apply the logical PG connection to newly added cells
  • Timing QOR's details


Hi I’m Designer of this blog.

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