In this post I am writing some frequently asked questions in cadence for layout profile
Q1. What are standard cells and why it is used?
Q2. Explain DRC and LVS.
Q3. Draw NAND gate layout.
Q4. What is importance of DRC and LVS?
Q5. Explain any two DRC errors.
Q6. Draw NAND gate and NOR gate schematic and which gate is preferred and why?
Q7. How to avoid Electro migration?
Q8. How mosfet operates when applied positive, negative and zero voltage at gate?
Q9. Implement XOR gate using CMOS.
Q10. What happens when the PMOS and NMOS are interchanged with one another?
Q1. What are standard cells and why it is used?
Q2. Explain DRC and LVS.
Q3. Draw NAND gate layout.
Q4. What is importance of DRC and LVS?
Q5. Explain any two DRC errors.
Q6. Draw NAND gate and NOR gate schematic and which gate is preferred and why?
Q7. How to avoid Electro migration?
Q8. How mosfet operates when applied positive, negative and zero voltage at gate?
Q9. Implement XOR gate using CMOS.
Q10. What happens when the PMOS and NMOS are interchanged with one another?
Q11. How does resistance
of the metal lines vary with increasing thickness and increasing length?
Q12. Why PMOS transistor generally
used to produce strong 1 while NMOS transistor generally used to produce strong
0?
Q13. What is difference
between Hard IP and Soft IP?
Q14. What is the purpose
of minimum area design rules?
Q15. Difference between
analog and digital layouts.
0 comments:
Post a Comment