Complete the blanks in the following questions with appropriate answer.
1. Find the output frequency "Fout" for the given input frequency "Fin". Set and clear are always tied off to zero.
Input Frequency (Fin) KHz=55
Output Frequency (Fout) KHz________.
2. A digital logic with "N" xor gate are connected in series as shown in the diagram.
Inputs of the first xor gate are: (1,X).
N = 50
1) Output of Nth xor-gate is ________.
2) Output "N+1" xor gate when passed through a not-gate is _______.
Note: if the answer is NOT(x) or inversion of x then mention it as either x' or x' or xbar
3. An interconnect protocol X is widely used in industry with below standards:
The maximum payload size that can be processed in packet in P bytes.
All intermediate transactions should end on naturally aligned P-byte address boundaries.
For request which exceed the supported payload size or any requests to unaligned addresses, the hardware splits the response packets in order to avoid any protocol violations.
There is an incoming read request from an end-point with read length=N byte at address location ADDR
P- Payload Max size =64
N- read length =202
ADDR (in hex)= 0x31121133
Given that there no protocol violations encountered the number of completion packets for the above read request is _____________.
4. In the given circuit Clk is running at frequency F1. Input A is square wave the frequency F2.
Counter increments by 1 only when input "Incr" is 1.
Assume ideal conditions with no clock skew or data transmission delays.
F1 (KHz) = 8
F2 (KHz) = 2
N1 = 7
N2 =10
1) What is the output of counter at clk cycle N1 ___________.
2) What is the output of counter at clk cycle N2 ___________.
5. Given the below circuit where Tbuf is the propagation delay of the buffer and Tor is the propagation delay of the OR gate in nSec.
Parameters
N ( nSec)= 25
Tbuf (nSec)= 2
Tor (nSec) = 4
How many buffers are required to filter reset glitches of width less than or equal to N nSec? ____________.
6. The device A and B are identical and both of them can measure the time gap between two posedge of the signal passing through it.
The circuit X contains flip-flops based binary counter.
An encounter was held by passing a clock signal clk_in into circuit X and clock signal clk_out was obtained at the output of circuit X.
Value of A (ns) = 2
Value of B (ns) = 128
Number of flip-flops in circuit X is __________.
7. A simple weighted arbiter unit is shown below with two Request lines (Req0, Req1) and corresponding two Grant lines (Gnt0, Gnt1).
The functional specification of the arbiter is as follows:
i. In any clock cycle, a valid request may be present on either or both Request lines.
ii. In any clock cycle, if there is a valid request on one or both Request lines, one (and only one) of the Grant lines will be asserted in response, in the same cycle. No grant slot will be left idle if a valid request is present.
iii. If both request lines are active. Req0 will have the higher priority for grant, except due to the fairness constraints below.
Fairness constraint 1: Gnt0 cannot be asserted for more than three cycles consecutively.
Fairness constraint 2: Gnt1 cannot be asserted for more than one cycle consecutively.
Test APIs are provided as below:
CreateRequests(Req0_val, Req1_val); At the next clock cycle, present the value Req0_val on Reqo line and Req1_val on Req1 line. (Req0_val, Req1_val could each be CheckGrants(Gnt0_val, Gnt1_val): At the current clock cycle, check the Grant lines for expected values Gnt0_val, Gnit1_val. If there is a mismatch with the expected error. (Gnt0_val. Gnt1_val could each be 0 or 1).
You are writing a test to check the fairness constraints. Fill in the expected arguments in the blanks based on the test that is being created to vently this design.
Note: While filling in the arguments, ensure that there are no white spaces between the arguments. For example-enter ab instead of "a,b" instead of " a , b "
reset and init():
CreateRequests(1,1);
CheckGrants (______________);
CreateRequests(0,1);
CheckGrants (______________);
CreateRequests(1,1);
CheckGrants (_______________);
CreateRequests(1,1);
CheckGrants (_______________);
8. An Interface obeys the characteristics of the waveform as provided below
As a verification Engineer, you are tasked with creating checkers for the interface specifications as provided.
Fill in the blanks with the accurate signal name from the interface specification for which the following checkers are being planned
1. Checking that ________gets_________(asserted/de-asserted) in the next clock cycle after _________(asserted/de-asserted).
2. Checking that_________ does not change throughout the time ________ is held high.
3. Checking that when ________ goes low ___________ also has to go low in the same clock cycle.
9. Line coverage is one of the metrics used to measure of the effectiveness of verification of an RTL design. It is a measure of what percentage of lines in the RTL code have been exercised by a verification test suite.
With reference to the chunk of code below, answer the following questions on line coverage.
if (parity== ODD || parity EVEN) begin
parity_bit <= compute_parity (data, parity);
tx <= {data, parity_bit, -parity_bit); end else begin
tx <= {data,2'b0};
end
if (revd_all) begin
start sending-1'b1;
end
Note: An input/stimulus vector is defined as one combination of the inputs: parity, data, rcvd_all. Parity could be {ODD, EVEN, NULL}, data is 16-bit wide, rcvd_all is 1-bit wide
Note: Lines with just key words (like else, begin or end) do not count towards coverable or covered lines.
The maximum line coverage (in percentage) achievable with a single stimulus vector is =___________.
The minimum line coverage (in percentage) achievable with a single stimulus vector is =_____________.
Note: Round off your answer to the nearest integer. For example: if the answer is 3.5, enter 4. if the answer is 3.49, enter 3
The minimal stimulus set that is needed to achieve 100% line coverage should contain the values as:
parity[1:0] =__________
rcvd_all 1
&&
parity[1:0] =___________
rcvd_all = 0/1
10. As a Verification engineer, you are tasked to identify System Verilog assertions that can be framed for a 2 master priority arbiter in which mst0 has more priority than mst1.
Here are some points for the specification
1. Grant gets asserted within 1-A clocks after request assertion
2. Master0 signals are Req0(o/p) and Gnt0(i/p).
3. Master1 signals are Req1(o/p) and Gnt1 (i/p).
A=3
Fill in the blanks with the accurate values for the SYSTEM VERILOG assertions that are planned
$rose(Req0) |->________________$rose(Gnt0);
$rose(Req1) &&________________| -> ___________$rose[____________];
11. For the following Verilog Code - Fill in the blanks with the right answers
always @(clk) begin
a=A
a<= B;
$display("Value of a is %0d",x);
b=C
b<=D;
#1:
$display("Value of b is %0d",b);
end
A=8
B=9
C=8
D=9
What would be the value of "a" displayed if this always block is simulated?
@First Cycle = Value of a is_______________
@Second Cycle = Value of a is_____________
What would be the value of "b" displayed if this always block is simulated?
@First Cycle = Value of b is_______________
@Second Cycle = Value of b is_____________
12. Assume that you have available a function ("DFS(graph, starting_node)") that performs a Depth First Search on a graph starting from a given starting node. Assume that the function traverses nodes in alphabetical order and also that the function skips the traversal of any node that has already been traversed. Below are the input graph and the starting_node:
Input graph:
Starting_node = J
The sequence of nodes visited=___________(Please specify the sequence as common separated list without any whitespaces, Eg if starting from node A: A,B,C,D,....)
13. Consider a sorted list of M integer elements. If a binary search is performed on the list, after N comparisons have been made, how many elements of the list would be left to search, in the worst case?
M= 32768
N= 6
The number of elements left to search=__________
14. Area of the chip increase every year by N %. If the area in year Y1 is X sq.units, what was the area in Y2.
N (%) = 5
Y1 = 2020
X (Sq.units) = 2300
Y2 = 2018
Area in year Y2___________
Note: Round it to the nearest integer.
Ex: If the answer is 25.5 then capture the output as 25 or 26. If it is 25.1 then capture the output as 25.
15. A computer system has a Double Date Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM). The data bus of the DDR SDRAM is Y bits wide and runs at X GHz.
X= 10
Y= 8
The total Data Bandwidth provided by the DDR SDRAM is ___________ Giga Bytes per second?(GBps)
16. A computer system has a L1 Data Cache, L2 Data Cache, and Main Memory unit connected as shown in the diagram. For a Program the Data hit rate in L1 and L2 Data Cache is H1 and H2 respectively (both H1, H2 are specified as a percentage). The time to access the data in L and L2 Data Cache is T1 and T2 ns respectively. The time to Access the Main Memory is T3 ns.
Note: The time to access L2 Data cache T2 includes the time to L1 Data Cache. So the time to access L2 should not be assumed as T1 + T2 ns. Similarly the time to access Main Memory is T3 ns and should not be assumed T1 +T2+T3 ns
H1= 80
H2= 40
T1= 10
T2= 30
T3= 100
The average Data Access time in ns is ______________.
17. Consider a non-pipelined processor with a clock rate of X GHz and average cycles per instruction of Z.
The same processor is upgraded to a pipelined processor with five stages but due to the internal pipeline delay, the clock speed is reduced to Y GHz.
X= 2.5
Y= 2
Z= 5
Assume there are no stalls in the pipeline. The speed up in throughput (Instruction per sec) achieved after pipelining the processor is_____________.
Note: Answer to two decimal place. Example (3.755 make it 3.75)
18. What is the output of the following program for given value of a?
void m()
{
static int x = a;
printf("%d", ++x);
}
void main()
{
m():
m():
m():
}
a=12
Answer:________________.
19. What will be the output of the following program for given values of a and b?
#include <stdio.h>
#define x a+b
main()
{
int i = x*x;
printf("%d", i);
}
a=2
b=2
Answer:____________.
20. Complete the blanks in the following question with the appropriate answer.
Given a function:
INTEGER func(INTEGER a, INTEGER b) {
if (b == 0)
return 1;
INTEGER temp = func(a, b / 2);
if (b%2!=0)
return temp * temp * a;
else
return temp * temp;
}
a=2
b=5
The value returned by the function is ____________.
21. The weights of the nodes of the following graph are given below. The length of a path on this graph is the sum of the weights of the nodes on the path. One can follow a greedy algorithm to find the shortest as well as the longest path from the start node to the finish node Assume that the greedy algorithm traverses to the next graph node based on the weights of only the immediate neighbors. To avoid loops, a node is not visited more than once by the algorithm. Traversal is allowed only in the direction indicated by the arrow.
A = 1
B = 2
C = 1
D = 2
E = 4
F = 1
G = 3
H = 5
The total node weight for the greedy shortest path = ____________.The total node weight for the greedy longest path =_____________.
The total node weight for the optimal shortest path =_____________. The number of nodes traversed (including the Start and End nodes) for the optimal shortest path=______________.
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