1. In complementary CMOS the Number of transistor required to implement an N fan-in gate is.
a) Moderate
b) High
c) Low
d) None of the above
10. The threshold voltage is
a) 2N
b) 2N+1
c) N
d) None of the above.
2. PMOS used as pull-up network because of.
a) pass weak 1
b) pass weak 0
c) pass strong 1
d) pass strong 0
3. When Kn>kp, threshold voltage moves closer to.
a) Zero
b) Infinity
c) midpoint value
d) supply voltage
4. When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, the transistors are operating in.
a) N-MOS is cut-off, p-MOS is in Saturation.
b) P-MOS is cut-off, n-MOS is in Saturation
c) Both the transistors are in linear region
d) Both the transistors are in saturation region
5. Reduction in power dissipation can be brought by.
a) increasing transistor area
b) decreasing transistor area
c)
d) decreasing transistor feature size
6. In the inverter chain the optimal number of stages for minimum delay equals to.
a) N
b) 2N
c) 2N+1
d) ln(F)
7. The overshoot in the transient response of the inverter due to.
a) Cgs
b) Cgd
c) Css
d) Cdd
8. The asymmetry of resistance value of CMOS inverter can be eliminated by.
a) Decreasing the width
b) Increasing the width
c) Increasing the length
d) Decreasing the length
9. CMOS inverter has output impedance.a) Moderate
b) High
c) Low
d) None of the above
10. The threshold voltage is
a) Increases on increasing temperature
b) May increase or decrease on increasing temperature depending upon other factors
c) Temperature independent
d)
For NMOS transistor which of the following is not true?
a) The substrate is of p-type semiconductor
b) Inversion layer or induced channel is of n type
c) Threshold voltage is negative
d) None of the above
12. With the potential difference between the source and the drain kept small (VDS is small), the MOSFET behaves as a resistance whose value varies __________ with the overdrive voltage.
a) inversely
b) linearly
c) Exponentially
d) None of the above
13. When the voltage across the drain and the source (VDS) is increased from a small amount (assuming that the gate voltage, VG with respect to the source is higher than the threshold voltage, Vt), then the width of the induced channel in NMOS (assume that VDS is always small when compared to the Vov).
a) Will remain as was before
d) Will become non uniform and will take a tapered shape with deepest width at the source
14. An n-channel MOSFET operating with Vov=0.5V exhibits a linear resistance = 1 kΩ when Vds is very small. What is the value of the device trans-conductance parameter kn?
a) 2 mA/V2
b) 20 mA/V
c) 0.2 A/V2
d) 2 A/V2
15. Find the threshold voltage of the inverter. Assume µn=545 cm2/V.S and µp=130 cm2/V.S Vtn=0.8 V and Vtp=-0.9 V and Vdd=3.3 V.
a) 1.5V
b) 1.4V
c) 1.3V
d) None of the above
16. Assume an inverter in the generic 0.25 mm CMOS technology designed with a PMOS/NMOS ratio of 3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W/L = 1.5). Compute the gain at VM (= 1.25 V).
d)
For NMOS transistor which of the following is not true?
a) The substrate is of p-type semiconductor
b) Inversion layer or induced channel is of n type
c) Threshold voltage is negative
d) None of the above
12. With the potential difference between the source and the drain kept small (VDS is small), the MOSFET behaves as a resistance whose value varies __________ with the overdrive voltage.
a) inversely
b) linearly
c) Exponentially
d) None of the above
13. When the voltage across the drain and the source (VDS) is increased from a small amount (assuming that the gate voltage, VG with respect to the source is higher than the threshold voltage, Vt), then the width of the induced channel in NMOS (assume that VDS is always small when compared to the Vov).
a) Will remain as was before
b) Will become non uniform and will take a tapered shape with deepest width at the drain
c) Will remain uniform but the width of the channel will increased) Will become non uniform and will take a tapered shape with deepest width at the source
14. An n-channel MOSFET operating with Vov=0.5V exhibits a linear resistance = 1 kΩ when Vds is very small. What is the value of the device trans-conductance parameter kn?
a) 2 mA/V2
b) 20 mA/V
c) 0.2 A/V2
d) 2 A/V2
15. Find the threshold voltage of the inverter. Assume µn=545 cm2/V.S and µp=130 cm2/V.S Vtn=0.8 V and Vtp=-0.9 V and Vdd=3.3 V.
a) 1.5V
b) 1.4V
c) 1.3V
d) None of the above
16. Assume an inverter in the generic 0.25 mm CMOS technology designed with a PMOS/NMOS ratio of 3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W/L = 1.5). Compute the gain at VM (= 1.25 V).
a) -27.5
b) -37.5
c) -47.5
d) None of the above
17. Calculate the power dissipation in a CMOS inverter. Consider a CMOS inverter with a load capacitance of CL = 2 pF biased at VDD = 5 V. The inverter switches at a frequency of f = 100 kHz.
a) 4µW
b) 2µW
c) 5µW
d) None of the above
18. We has a total of four toggles of the output over the duration of eight clock cycles. What is the activity factor?
a) 25%
b) 50%
c) 75%
d) None of the above
19. Compute the optimal inverter fanout ratio f for a three-stage inverter chain with Cload = 200 fF and Cin = 1 fF.
a) 5.8
b) 5.4
c) 6.2
d) None of the above
20. Compute the charge-sharing effects for the following cases assuming 0.13 um technology parameters. For C1, = 100 fF, C2 = 20 fF, V1 = 0, V2 = 1.2 V.
a) 0.3V
b) 0.1V
c) 0.2V
d) None of the above
Answers: 1. a 2. c 3. a 4. d 5. a 6. d 7. b 8. b 9. c 10. d 11. c 12. b 13. c 14. a 15. b 16. a 17. c 18. a 19. a 20. c
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b) -37.5
c) -47.5
d) None of the above
17. Calculate the power dissipation in a CMOS inverter. Consider a CMOS inverter with a load capacitance of CL = 2 pF biased at VDD = 5 V. The inverter switches at a frequency of f = 100 kHz.
a) 4µW
b) 2µW
c) 5µW
d) None of the above
18. We has a total of four toggles of the output over the duration of eight clock cycles. What is the activity factor?
a) 25%
b) 50%
c) 75%
d) None of the above
19. Compute the optimal inverter fanout ratio f for a three-stage inverter chain with Cload = 200 fF and Cin = 1 fF.
a) 5.8
b) 5.4
c) 6.2
d) None of the above
20. Compute the charge-sharing effects for the following cases assuming 0.13 um technology parameters. For C1, = 100 fF, C2 = 20 fF, V1 = 0, V2 = 1.2 V.
a) 0.3V
b) 0.1V
c) 0.2V
d) None of the above
Answers: 1. a 2. c 3. a 4. d 5. a 6. d 7. b 8. b 9. c 10. d 11. c 12. b 13. c 14. a 15. b 16. a 17. c 18. a 19. a 20. c
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