During fabrication the chips on the same die may suffer from variations due to process, voltage or temperature change, thus transistors can be faster or slower in different dies. To compensate the variation, static timing analysis(STA) introduces a concept called On Chip Variation(OCV). During design time, extra timing margins are added in timing analysis.
OCV has been evolved to Advanced On Chip Variation(AOCV), or even Parametric On Chip Variation(POCV).
On Chip Variation(OCV): This concept is related to fabrication process, these variation related to fabrication steps : first is Etching and second is oxide thickness.
There are two types of variation:
Global Variation: These variations are die to die or inter-chip variation. They depend on Process, voltage and temperature.
Local Variation: These variation are intra-chip variations and local variation are taken by derates, timing derates are multiplied by cell delays and wire delays to account OCV.
Now we will see how OCV is related to fabrication.
Etching: Etching is one of the sources of variation, which is used the define the structure of a transistor. In practical case the width and length of transistor is different from the expected W and L ratio. The small change for one transistor will result in big impact on chain of billion of transistors.
From the above figure we observe that ideal case is different from practical case.Let us take W and L in ideal case.It is different from W and L in actual case.
Now we will see  how this small change in W/L ratio affects cell delays.As we know the formula of drain current,
         Drain current (Id) = uCox(W/L)[(Vgs-Vth)Vds-(1/2)Vds^2]
Where u is mobility of charge carriers,Cox is capacitance per unit area,W is width of channel,L is channel length,Vgs is gate to source voltage,Vth is threshold voltage and Vds is drain to source voltage.
We can observe from drain current equation Id is directly proportional to (W/L), when we think of a capacitor at the output of an inverter then capacitor charging depends on the amount of current that is flowing it.If drain current changes the amount of time taken by capacitor definitely changes.
If drain current (Id) is high then capacitor takes less amount of time to charge and hence delay is minimum.
If drain current (Id) is low then capacitor takes huge amount of time to charge and hence delay is maximum.
Hence we can say that delay decrease with increase in current and vice versa.
Oxide thickness: Oxide thickness is another source of variation,In practical case the oxide thickness is not uniform along the channel.
We know the drain current equation,
Drain current (Id) = uCox(W/L)[(Vgs-Vth)Vds-(1/2)Vds^2]
where Cox=εox/tox ,Id is inversely proportional to tox.
If the value of tox changes the value of drain current is also changes.Now we will see how delay of cell is related to W/L and tox from formula point of view, we know that delay of a cell depends on resistance(R) and capacitance(C) and from ohm's law resistance varies as current changes.
Delay (tpd)=function(R,C)=f(Id)=f(tox,W,L)
As a result of OCV, some cells may be fast or slow than expected. If these variations are not accounted, results may be pessimistic and can lead to setup or hold violations. In order to model these, we introduce derates. Timing derates are multiplied with the net delay and cell delay for the launch and capture clock paths. This is given as say x%.
How to calculate timing slack using OCV:
Setup Analysis: While calculating the setup analysis we need to take late derate along the launch path and early derate along the capture path.
Arrival Time: Arrival time includes addition of cell and wire delays along the launch path.
Arrival Time(AT) = wire1 delay * late derate + clk to q * late derate + wire2 delay * late derate + inverter delay * late derate + wire3 delay * late derate.
Arrival Time(AT) = 0.1*1.1 + 0.2*1.1 + 0.2*1.1 + 3*1.1 + 0.4*1.1
Arrival Time(AT) = 4.29 ns
Required Time:
Required Time(RT) = Tclk-Tsetup + [Twire delays*early derate + Tcell delays*early derate]
RT = 2-0.2+[0.3*0.9+2*0.9+0.4*0.9]
Required Time(RT) = 4.23 ns
Setup Slack = RT-AT=4.23-4.29= -0.06 ns (-ve slack).
Negative slack indicates setup violation.
Hold Analysis: While calculating the hold analysis we need to take early derate along the launch path and late derate along the capture path.
Arrival Time(AT) = wire1 delay * early derate + clk to q * early derate + wire2 delay * early derate + inverter delay * early derate + wire3 delay * early derate.
Arrival Time(AT) = 0.1*0.9 + 0.2*0.9 + 0.2*0.9 + 3*0.9 + 0.4*0.9 = 3.51 ns
Required Time:
Required Time(RT) = Thold +Twire delays*late derate + Tcell delays*late derate
Required Time(RT) = 0.1 + 0.3*1.1 + 2*1.1 + 0.4*1.1 = 3.07 ns
Hold  Slack = AT-RT=3.51-3.07 = 0.44 ns(+ve slack) which shows hold condition is met.
Case2(without ocv):
Setup Analysis:
Arrival Time:
Arrival Time(AT) = wire1 + clk to q + inv delay + wire3
Arrival Time(AT) = 0.1+0.2+0.2+3+0.4 = 3.9 ns
Required Time:
Required Time(RT) = Tclk-Tsetup + Twire delays + T cell delays
Required Time(RT) = 2-0.2+0.3+2+0.4 = 4.5 ns
Setup Slack = RT-AT = 4.5-3.9 = 0.6 ns(+ve slack) which shows setup condition is met.
Hold Analysis:
Arrival Time:
Arrival Time(AT) = wire1 + clk to q + inv delay + wire3
Arrival Time(AT) = 0.1+0.2+0.2+3+0.4 = 3.9 ns
Required Time:
Required Time(RT) = Thold + Twire delays + T cell delays
Required Time(RT) = 0.1+0.3+2+0.4 = 2.8 ns
Hold Slack = AT-RT = 3.9-2.8 = 1.1 ns(+ve slack) which shows hold condition is met.
From above two cases we conclude that we should always consider the derates and apply them to avoid timing violation.
Advanced On chip Variation(AOCV): In case of OCV constant derates are applied across the timing path.But in AOCV we multiply cell and wire delays with different derate factors depending on the distance and depth.AOCV is represented by a two dimensional table: the derate value of a cell is determined by logic depth and distance.
For smaller path depths OCV gives optimistic results when compared to AOCV.For larger path depths OCV tends to be more pessimistic than AOCV(AOCV gives accurate values).
Parametric On Chip Variation(POCV): Below 10nm technologies AOCV cannot reduce pessimism hence to reduce the pessimism at lower technology nodes POCV was introduced.Here cell delay is calculated based on delay variation of cell, delay variation denoted by sigma and delay is denoted by u.POCV models a cell delay using Gaussian distribution directly, instead of adding a derate value. Cell delay is calculated from a parameter, which is extracted from either library, or POCV table.


Hi I’m Designer of this blog.

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