1. The logic function implemented by the given combinational circuit.
2. The output voltage of given circuit is.
a)
b)
c)
d) None of the above
3. The logical effort corresponding to input A.
a) 1
b) 2
c) 3
d) 4
4. The time constant at the output node Vout is
a) 0.64
b) 0.44 ns
c) 0.54 ns
d) None of the above
5. The equivalent (W/L) ratio for pull down network is .if (W/L)n =10.
a) 12
b) 13
c) 14
d) 15
6. What is the correct order of progressive scaling?
a)
b)
c) M1>M2>M3>MN
7. For two input NOR gate the transition probability is
a) 2/16
b) 1/16
c) 3/16
d) 5/16
8. The Optimal stage effort h for given circuit is
a) 1.93
b) 1.37
c) 1.39
d) 4.39
9. The delay of given circuit is
a) 12
b) 15
c) 14
d) 13
10. The value of X in the given circuit is
a) 14.5
b) 12.5
c) 13.5
d) None of the above
11. The average logical effort of the given circuit is
a) 4
b) 1
c) 2
d) 3
12. The logical effort of pull-up network in this circuit is
a) 2/3
b) 3/2
c) 4/3
d) None of the above
13. In the sequential circuit shown below,if the initial value of the output Q1Q0 is 00,what are the next four.
a) 11,00,10,00
b) 00,10,01,11
c) 00,01,10,11
d) 11,10,01,00
14. Latch is a device with__.
a) One stable state
b) Two stable state
c) Three stable state
d) None of the above
15. Pipelined circuits can be constructed using
a) edge-triggered registers
b) level-sensitive latches
c) Both a and b
d) None of the above
16. If the maximum delay of the combinational block is 1 ns, set up time is 1 ns and minimum delay of the register is 1 ns, then the minimum clock period of the master clock is
a) 4 ns
b) 5ns
c) 3ns
d) None of the above
17. When a positive latch and negative latch are cascaded, it forms a
a)
b) Transmission Gate
c)
d) None of the above
18. In a pipelined architecture, if there are three block which are pipelined the operating frequency is
a) Increases by three times
b) Increases by two times
c) Decreases by three times
d) None of the above
19. In a latch based clocking, if TCLK is the time period of the master clock, then the amount of time allotted for combinational computation is
a) TCLK
b) TCLK/2
c) 2TCLK
d) None of the above
20. The difference in timing between Read Request and the moment is available at the output is defined as
a) Write Access Time
b) Write Cycle Time
c)
d) Read Cycle time
21. If the combinational block delay is ideally considered to be zero and the two registers have a delay of 1 ns each, then the maximum frequency of operation for such a system is
a) 1.5 × 10*9 Hz
b) 0.5 × 10*8 Hz
c) 1.5 × 10*8 Hz
d) 0.5 × 10*9 Hz
22. When the clock and the data path are in the same direction
a) Positive Skew is observed
b) Negative Skew is observed
c)
d) No skew is observed
23. For an edge triggered clock, the sampling of a data is done at
a) Rising edge
b) Falling edge
c) Both a and b
d) None of the above
24. The drawback of pulse latched is
a)
b)
c) De
d) De
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