Signal Integrity

Signal integrity
Signal integrity is the ability of an electrical signal to carry information reliably and resist the  effects of high frequency electromagnetic interference from adjacent signals. Crosstalk and antenna effect and electromigration are signal integrity issues.
Crosstalk

Crosstalk is the undesirable electrical interaction between two or more adjacent nets due to capacitive cross-coupling.
Switching of the signal in one net (aggressor) can interfere neighbouring net (victim)due to cross coupling capacitance this is called cross talk.Cross talk may lead to setup and hold violation.

Crosstalk has two effects.

1. Crosstalk Noise: During the transition on aggressor net causes a noise bump or glitch on victim net. This noise is known as crosstalk noise.In deep submicron technologies noise plays an important role in terms of functionality or timing of device.
2. Crosstalk Delay: It implies the delay happening in the output transition of victim due to transition of aggressor. Crosstalk delay depends on the switching direction of aggressor and victim net because of this either transition is slower or faster of victim net.
Aggressor is a net which creates impact on the other net.
Victim is a net which is impacted by aggressor net.
Types of Crosstalk:

Positive crosstalk: The aggressor net has rising transition at the same time when the victim net has a falling transition. The aggressor net switching in opposite direction increase delay for victim.The positive crosstalk impacts the driving cell as well as the net interconnect the delay for both gets increased because charge required for the coupling capacitance is more.

Negative crosstalk: The aggressor net is rising transition at the same time as the victim net. The aggressor net switching in same direction decrease delay of the victim. The positive crosstalk impacts the driving cell as well as the net interconnect - the delay for both gets decreased because charge required for the coupling capacitance is less.

• When the signal through the aggressor net transition from one end to another end charge gets stored in the coupling capacitance electrical interference and at the same time the charge stored in the capacitance will discharge on the victim signal.
• When two nets in parallel and the spacing between the nets is less than capacitance is more.
• Crosstalk depends on  whether the signals are switching at the same time or not. Transition at the same time in opposite directions is the worst cross talk and to resolve this we  do shifting of timing window.
• Crosstalk delta shows how much signal degraded because of noise.Victim nets get affected based on the rise and fall transition.

1. When both aggressor and victim is rising.

2. When both aggressor and victim is falling.

3. When aggressor is rising and victim is falling.

4. When aggressor is falling and victim is rising.

Crosstalk effects on timing analysis:

• In data path when aggressor net and victim net transition are in the same direction,victim transition becomes faster and as such data arrives early which may lead to hold violation.
• In clock path when aggressor net and victim net transition are in the same direction,victim transition improves which makes clock to arrive faster as such leading to setup violation.
• In clock path when aggressor net and victim net transition are in the different direction,victim transition becomes slow then data arrives slowly which may lead to setup violation.
• In clock path when aggressor net and victim net transition are in the different direction,victim transition becomes slow it makes the clock to arrive slowly which may lead to hold violation.

How to fix the Crosstalk

• Double Spacing:Increase the spacing between the aggressor net and victim net.
• Shielding: Placing a ground net in between the aggressor net and victim net so that the voltage will discharge through this and save from crosstalk issue.
• Buffer Insertion: Insertion of buffers will boost the strength of the victim net.
• Use multiple vias means less resistance then less RC delay.
• Shifting the timing window.
• Increased the drive strength of victim net.
• Decrease the drive strength of aggressor net.

In detail click here:

Electromigration

• Due to high current density, the electrons in the metal moved with high acceleration. And these electrons transfer their momentum to other atoms and the atoms get displaced from their original position and might create voids and hillocks.Hillocks will create shorts and voids will create opens between metal layers.
  

How to fix the Electromigration

• Increase the width of wire
• Buffer insertion
• Switch the net into higher metal layer
• Keep the wire length short

Antenna Effect

• During the fabrication of MOS integrated circuits, especially at the time of plasma etching, there will be a chance of collecting more charges at the gate and causes damage to the gate oxide layer since it is very thin. This condition is known as Antenna effect.
• Fabrication lab normally supply antenna rules, which are rules that must be obeyed to avoid this problem. A violation of such rules is called an antenna violation.
• The word antenna is something of a misnomer in this context—the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to/from electrical currents.
• The extra induced charge carriers might be too much for the gate to handle and the thin oxide layer is as such damaged. This is the reason antenna ratio is more prominent in higher technology nodes as the shrinking technology causes shrinking in the oxide width too which cause more impact to damage.Fig.1 shows the NMOS transistor where we can see the gate with the thin oxide layer that breaks down due to the electrons which get accumulated near the channel region during fabrication process.

How to solve antenna violation

To fix the antenna violation issues in our design our main should be to reduce the antenna ratio value.

• Metal jumper: Break signal wires and route to upper metal layers by jumpers. Jumper insertion breaks the long wire which is connected gate and route to upper metal layer. So it becomes short and less capable of collecting charge. If the antenna violation happens at a metal layer, always use higher metal layers as metal jumper since all the lower layers are already fabricated at that moment.
  
• Diode insertion : Add the reverse biased diode near gate input where violation occurs on a net provides a discharge path to the substrate which saves the gate of the transistor. Adding diode increases the area and also the capacitance which leads to increase in delay. Mostly n type diode is preferred over p type as the p type needs extra biasing of their nwell.
  

• Change the order of the routing layers. If the gate(s) immediately connects to the highest metal layer, no antenna violation will normally occur.

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Hi I’m Designer of this blog.