1.What is pipelining?
2.For a pipeline with 'n' stages, what’s the ideal throughput? What prevents us from achieving this ideal throughput?
3.What is a pipeline hazard? What are the different types of hazards in a pipelined microprocessor design?
4.What are Branch Prediction and Branch Target Prediction?
5.How do you handle precise exceptions or interrupts?
6.What is Virtual Memory?
7.What is Cache Coherency?
8.What is MESI protocol?
9.What is the difference between a RISC and CISC architecture?
10.What is the difference between Von-Neumann and Harvard Architecture and which would you prefer?
11.Explain the concept of Little Endian and Big Endian formats in terms of memory storage?
12.What are the different types of registers implemented in a CPU?
13.What are the different types of addressing modes for an instruction?
14.What is a cache miss or hit condition?
15.What is the concept of paging?
16.What is the concept of cache memory?
17.What is a TLB (Translation lookaside buffer)?
18.What is meant by page fault?
19.If a CPU is busy executing a task, how can we stop it and run another task?
20.What is the difference between a conditional branch and unconditional branch instruction?
21.What is meant by memory mapped I/O?
22.What is a vectored interrupt?
23.What are interrupts and exceptions and how are they different?
24.What is the difference between a virtual memory address and a physical memory address?
25.What is the difference between snoop based and directory based cache coherency protocol?
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