VLSI Design Flow

The chip design includes different types of processing steps to finish the entire flow. For anyone, who just started his career in VLSI industry has to understand all the steps of the VLSI design flow. Each and every step of the VLSI design flow has a dedicated EDA tool that covers all the aspects related to the specific task perfectly.All the EDA tools can import and export the different file types to help making a flexible VLSI design flow that uses multiple tools from different vendors.The VLSI design flow is shown in the figure below.

VLSI Design Flow
Here is a brief description of each step in VLSI Design Flow:
System Specification
  • The first step of VLSI Design Flow is system specifications. System specification is a high level representation of the system. The factors to be considered in this process include performance, functionality and interface.
Architectural Design
  • This is step where main work start with the help of system specification.
  • Design engineer design the architecture according to system specification.
Functional and Logic Design
  • In this step functionality of design are identified.
  • It specify the hardware implementation of system functionality.
  • The outcome of functional design is usually a timing diagram.
  • In logic design step,register allocation, logic and arithmetic operations of the design that represent the functional design  are derived and  tested this description is called RTL description. RTL stands for register transfer level.In this step, system specification is expressed in hardware description language (HDL) such as Verilog and VHDL.
  • RTL description is used for simulation to test the functionality with the help of EDA tools.
  • Functional verification is performed to ensure the RTL design is done according to the specifications
  • RTL code is converted to gate level netlist using synthesis tools. Netlist is a description of the circuit in terms of gates and connections between them.
  • To verify whether the synthesis tool has correctly generated the gate-level netlist a verification should be done.
Circuit Design
  • In this step circuit is designed based on the logic design. The Boolean expressions are converted into circuit representation by taking into consideration the power and speed requirement of original design.
  • Circuit simulation is used to verify the correctness and timing of each component.
  • Diagram consists circuit elements such as gates and transistors.
Physical Design
  • In this step the netlist is converted into physical geometric representation.
  • Layout is representation of an IC in terms of planar geometric shapes which correspond to the patterns of metal oxide or semiconductor layers that make up the components of the Integrated circuit. Layout is designed by eda tool such as cadence virtuoso.
  • Physical design is a very complex step therefore it is divided into sub steps such as floor planning, placement,clock tree synthesis, routing etc and timing analysis checks are formed in each and every step during physical design.
  • Floor planning which is a process of placing the various blocks and the I/O pads across the chip area based on the design constraints.
  • Placement of physical elements within each block and integration of analog blocks or external IP cores is performed.
  • When all the elements are placed, a global and detailed routing is running to connect all the elements together.
  • Output of layout is GDSII file which is given to the foundry to fabricate the chip.The layout should be done according to foundry design rules.
Physical Verification and Signoff
  • In this step we perform physical verification checks such as Layout Vs schematic (LVS) and Design Rule check (DRC).
  • DRC verifies whether the given layout satisfies the design rules provided by the fabrication team. DRC checks are nothing but physical checks of spacing rules between metals, minimum width rules, via rules etc.
  • LVS is a major check in the physical verification stage.Layout is compared with the schematic for verifying whether their functionally match or not. If match, then the LVS reports clean.
  • After physical verification step the design is ready for fabrication. Tape out is the final result of the design process for integrated circuits before they are sent for manufacturing. The tape-out is specifically the point at which the graphic for photo mask of the circuit is sent to foundry. 
  • Fabrication process consists of several steps involving wafer growth,epitaxial growth masking,etching,doping,deposition,and diffusion of various materials on the wafer. During each step one mask is used.
Packaging and Testing
  • Each of the wafers contains hundreds of chips.These chips are separated and packaged by a method called scribing and cleaving.The chips that are failed in electrical test are discarded.
  • Each chip is packaged and tested to ensure that it meets all the design specifications and functions  properly.


Hi I’m Designer of this blog.

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