Testing of VLSI Circuits

Why do we need testing?
  • Fabrication process are becoming more and more complex ,design are coming closer  together and becoming smaller and thinner.So there is chances of two wires touching each other, these are the sources of errors or faults.
  • Possibility of faults during fabrication.
  • Necessary to test each and every chip.
  • Billions of transistor is present in modern vlsi chip.
  • So objective of testing is to determine the presence of faults or errors in chip.
  • It is caused during manufacture or the use of devices.
  • A defect is an unintended difference between the implemented hardware and its intended design.
  • A representation of a physical defect at the abstracted function level.
  • A wrong output signal produced by a defective circuit.
  • It is caused by a fault or a design error.
Objective of Testing
  • Testing is used to determine the presence of faults in chip.But sometimes testing is not guarantee that a chip is free from any faults because of many issues such as environmental variations like temperature, humidity, pressure. 
  • So,it is not really possible to test against all possible environmental variations.
  • So we usually use verification along with testing.
  • But verification and testing have different objective.
Verification Vs Testing
  • Testing tries to guarantee the correctness of manufactured chips.
  • Responsible for quality of devices.
  • Testing has to be performed on every manufactured device.
  • Test step process:  a) Test Generation b) Test Application.
  • Verification verifies correctness of the design.
  • Responsible for quality of design.
  • Verification performed once before the actual manufacturing of chips.
  • Performed by simulation, hardware emulation or formal methods.
When to do testing?
  • Testing can be carried out at various level:
  • At the chip level when the chips are manufactured.
  • At the board level when the chips are integrated on the boards.
  • At system level when several boards are assembled together.
  • Rule of thumb: Detect a fault early reduces the cost of testing
  • Empirical rule says that it is 10 times more expensive to test a device as we move to the next higher level for example, chip level to board level, board level to system level.
Sources of faults
  • During fabrication process like we actually fabricate some rectangular patterns on the surface of the silicon. So, some of such rectangular patterns may be missing this is called missing contact window.
  • Accidentally some diffusion poly silicon layers might overlap during to parasitic transistors.
  • Defects in the materials on which the chips are getting fabricated like silicon substrate, there can be some cracks or imperfections,surface impurities etc.
  • Because of ageing and defects during packaging.
Types of faults:
Faults is divided into two types:
  • Permanents Faults: They change the behavior of a chip in a way which is not dependent on time which is permanent.It is easy to detect.
  • Non Permanents Faults: Occur randomly and at unpredictable times and for unpredictable duration. It is difficult to detect.
Fault Coverage
  • The measure of the ability of a test set T to detect a given set of faults.
  • Fault Coverage (FC)= No. of detected faults/Total No of faults.
  • It can be determined by fault simulation.
Defect Level
  • The fraction of devices that pass all the tests but still contain faults.
  • Defect level(DL) = 1-Y^(1-FC) where Y is
  • Yield (Y) = No. of good dies per wafer/No. of dies per wafer.
why we need a fault model?
  • Number of physical defects in a chip ca be too many, it is impossible to count and analyse all possible faults.
  • We abstract this physical defects and we define some logical fault models.
  • Makes test generation and fault simulation possible.
  • We can evaluate fault coverage and compare test vectors.
Fault models can be defined at various levels of abstraction.
  • Behavioral level fault model
  • Functional level fault model
  • Structural level fault model
  • Switch level fault model
  • Geometric level fault model
Structural level fault model
Structural level fault model, which is the most widely used and common.Circuit is specified as a netlist typically at the level of gates and flip flops.There are two most popular structural fault models which are used the first one is stuck at fault model and the second one is bridging fault model.
1.Stuck at fault model
  • Some of the circuit lines are permanently stuck at logic 0 or logic 1.
  • Single stuck at fault: Only one line of circuit has a stuck at fault.Most widely used in vlsi industry.For example: two input AND gate, number of single stuck at fault is 6.For a circuit with k lines total number of single stuck at faults is 2k.
k=12 Number of single stuck at faults is 24
  • Multiple stuck at fault: Any number of circuits lines can have stuck at faults.For a circuit with k lines can have 3^k –1 possible stuck line combinations as each line can be one of the three states: s-a-0, s-a-1 or fault free.
k=12 Number of multiple stuck at faults is 531440


2.Bridging Fault model
  • Two or more normally distinct lines are shorted together.
  • The logic value of the shorted net may be modeled as 1-dominant (OR bridging), 0-dominant (AND bridging).

Switch level fault model
  • Switch level means at the level of the transistors,MOS transistor is considered an ideal switch and two types of faults are modeled:Stuck-Open and Stuck-Short faults.
  • In stuck-open fault a single transistor is permanently stuck in the open state.
  • In stuck-short fault a single transistor is permanently shorted irrespective of its gate voltage.


Hi I’m Designer of this blog.

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