VLSI Physical Design Flow

The chip design includes different types of processing steps to finish the entire flow. For anyone, who just started his career in vlsi physical design domain has to understand all the steps of the vlsi physical design flow. Each and every step of the VLSI physical design flow has a dedicated EDA tool that covers all the aspects related to the specific task perfectly.All the EDA tools can import and export the different file types to help making a flexible VLSI design flow that uses multiple tools from different vendors.
Physical design is process of transforming netlist into layout [GDSII].Main steps in physical design are floorplanning,placement of all logical cells, clock tree synthesis & routing. During this process of physical design area, timing, power, design & technology constraints have to be met.Further design might require being optimized with respect to area, power,timing and performance.The VLSI physical design flow is shown in the figure below.
VLSI Design Flow
VLSI Physical Design Flow          

Here is a brief description of each step in VLSI Physical Design Flow:
Import Design or NetlistIn
  • Import design or netlistIn is first step in physical design flow.
  • In this step we import all design files and constraints files such as netlist, sdc, upf,def,technology file,logical and physical libraries and tlu+ file.
  • This is the major step in physical design flow.In this step we have netlist which describes the design and the various blocks of the design and the interconnection between the different blocks. The netlist is the logical description of the ASIC design. Floorplan is the physical description of the ASIC design. In floorplanning we are mapping the logical description of the design to the physical description.
  • Floorplanning is the process of placing blocks/macros in the chip/core area.
  • Determine width and height of core and die.
  • Determine location of predefined cell/macros.
  • Determine I/O pin placement.
  • Creating the Pad Ring for the Chip.
  • Objective of floorplanning are to minimize the area and delay. 
  • Placement is the process of placing standard cells in the design.The tool determines the location of each standard cell on the die.The tool places these cells based on the  algorithms which it uses internally.
  • Placement does not just place the standard cells available in the synthesized netlist. It also optimizes the design. Placement also determines the routability of your design.
  • Placement will be driven by different criteria like timing driven, congestion driven, power optimization.
  • Objective of placement is to optimize the area,timing, power and minimal timing DRCs and minimal cell and pin density.
  • The placement should be routable.
  • Clock Tree Synthesis (CTS) is a process which make sure that the clock signals distributed uniformly to all sequential elements in a design.
  • CTS is the process of insertion of buffers or inverters along the clock paths of design in order to achieve minimum skew.
  • Objective of CTS to meet clock tree design rule constraints such as maximum transition, maximum load capacitance and maximum fanout and to meet clock tree targets such as minimum skew and minimum insertion delay.
  • Routing is the stage after CTS ,it is a process determines the precise paths for interconnections.
  • Routing is nothing but connecting the various blocks in the chip with one an other.
  • After CTS, we have information of all the placed cells, blockages, clock tree buffers/inverters and I/O pins.This information is important for tool to complete all the connections defined in netlist.
  • In routing stage, metal and vias are used to create the electrical connection in layout defined by logical connections present in netlist.
  • Objective of routing to meet the timing constraints, no LVS errors,no DRC errors and minimize the total wire length.
  • There are many stages in routing process: a)Global routing b)Track assignment c)Detailed routing d) search and repair.
Physical Verification and Signoff
  • After routing stage your layout is ready.In this stage we have to perform signoff checks for example physical verification check,timing analysis,logical equivalence checking.
  • We perform physical verification checks such as Layout Vs schematic (LVS) and Design Rule check (DRC) and Electrical Rule Check(ERC) and antenna check.
  • Equivalence check will compare the netlist we started out with (pre-layout/synthesis netlist) to the netlist given by the tool after PnR(post layout netlist).
  • DRC verifies whether the given layout satisfies the design rules provided by the fabrication team. DRC checks are nothing but physical checks of spacing rules between metals, minimum width rules, via rules etc.
  • LVS is a major check in the physical verification stage.Layout is compared with the schematic for verifying whether their functionally match or not. If match, then the LVS reports clean.


    Hi I’m Designer of this blog.

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