1. Estimate rising and falling prorogation delays of a 2-input NAND driving „h‟ identical gates using Elmore Delay
a) Rising = (6 + 4h)RC Falling = (7 + 4h)RC
b) Rising = (6 + 4h)RC Falling = (6 + 4h)RC
c) Rising = (7 + 4h)RC Falling = (7 + 4h)RC
d) Cannot be determined
2. In a CMOS level implementation, the number of transistors required to build a Nand gate is larger than that of and gate
a) True
b) False
3. Estimate the frequency of an N-stage ring oscillator with g = 1, h = 1, p = 1 and d = 2
a) 1/8N
b) 1/2N
c) 1/4N
d) None of the above
4. Minimum delay of N stage path is
a) D = NF powerof(N) + P
b) D = NF powerof(1/N) + P
c) D = NF + p
d) None of the above
5. When delays are small, power consumption is
a) High
b) Low
c) Cannot be determined
d) Does not change
6. When transistors switch, both NMOS and PMOS networks may be momentarily ON at one, which leads to
a) DIBL current
b) GIDL current
c) Short Circuit current
d) None of the above
7. The time difference between the input signal crossing a 0.5VDD and the output signal crossing its 0.5 VDD when the output signal is changing from low to high is
a) Propagation delay low-to-high (Fall Propagation)
b) Rise Transition Time
c) Fall Transition Time
d) Propagation Delay low-to-high (Rise Propagation)
8. Switching point voltage of a cell refers to
a) Voltage in triode condition
b) Voltage at nominal condition
c) Voltage at cutoff condition
d) Point on VTC where VOut = Vin
9. The largest percentage of static power results from source-to-drain Sub-threshold leakage. This is caused by
a) Reduced threshold voltages that prevent the gate from completely turning off
b) Increased threshold voltages that prevent the gate from completely turning off
c) Reduced threshold voltages that prevent the gate from completely turning on
d) Increased threshold voltages that prevent the gate from completely turning on
10. Logical effort is a method to make the following decisions
a) Uses a simple model of delay and allows „back-of-the envelope‟ calculations
b) Helps making rapid comparisons between alternatives
c) Emphasizes remarkable symmetries
d) All of the above
11. Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.
a)True
b) False
12. Delay has 2 components, d = f + p, f and p stands for?
a) f – Gate Delay and p – propogational Delay
b) f – Effort Delay and p - Parasitic Delay
c) f – Fall Delay and p - propogational Delay
d) None of the above
13. For an NMOS operation, one of the following points are true
a) In Cut-off, Vin < Vtn – In Linear, Vin > Vtn and In Saturated, Vout < Vin – Vtn
b) In Cut-off, Vtn > Vin – In Linear, Vin > Vtn and In Saturated, Vout > Vin – Vtn
c) In Cut-off, Vin < Vtn – In Linear, Vin > Vtn and In Saturated, Vout > Vin – Vtn
d) In Cut-off, Vin < Vtn – In Linear, Vin <Vtn and In Saturated, Vout > Vin – Vtn
14. The group of primitive cells which are used to build larger circuits is called
a) Standard Cells
b) Dummy cells
c) Macro cells
d) None of the above
15. The time it takes a driving pin to make a transition from K(VDD) to (1-K)VDD value is
a) Propagation delay
b) Rise transition time
c) Fall transition time
d) Settling time
16. Register re-timing works by
a)Moving registers through the cones of logic where end-to-end functionality of the circuit is unchanged
b) Splitting of merging registers through the cones of logic where end-to-end functionality of the circuit is unchanged
c) Merging registers through the cones of logic where end-to-end functionality of the circuit is unchanged
d) Moving, Splitting of merging registers through the cones of logic where end-to-end functionality of the circuit is unchanged
Answers: 1.a 2.a 3.c 4.b 5.a 6.c 7.d 8.d 9.a 10.d 11.a 12.b 13.c 14.a 15.b 16.d
0 comments:
Post a Comment