These type of questions asked in written test or online test of product and service based companies like synopsys, nvidia, cadence, nxp, mentor graphics, qualcomm, xilinx, amd and intel etc.
Q1. From the following options, how will you increase the conductivity of pure silicon?
a) Doping Group -V Elements
b) Doping Group – III elements
c) Both a and b
d) None of the above
Q2. What happens when NMOS gate is at a low voltage?
a) P-Type body is at low voltage
b) Source-body and drain-body diodes are off
c) No current flows, transistor is off
d) All of the above
Q3. State whether the following statement is either True or False. Pure silicon has no free carriers and conducts poorly.
a) True
b) False
Q4. The voltage at the gate on NMOS is _________ when there is a positive charge on gate of the MOS capacitor and transistor is ON.
a) HIGH
b) LOW
Q5. When current flows from the drain to source and if Ids increases with Vds, then the transistor would be in ______ region.
a) Cut-off
b) Active
c) Saturation
d) Linear
Q6. What are the characteristics of NMOS transistor in the cut-off region?
a) Negative voltage on the Gate attracts holes in substrate towards oxide
b) Electrons are pushed deeper into the substrate
c) Both a and b
d) None of the above
Q7. Estimate the delay of a fan-out of 1 inverter using RC delay model.
a) 6RC
b) 8RC
c) 4RC
d) 2RC
Q8. If the width of a transistor increases, the current ________ and its gate capacitance ______.
a) Increases and Increases
b) Decreases and Increases
c) Increases and Decreases
d) Decreases and Decreases
Q9. If Vt increases, then the ____.
a) Current Ids increases and speed of operation will be higher.
b) Current Ids decreases and speed of operation will be higher.
c) Current Ids decreases and speed of operation will be slower.
d) Current Ids increases and speed of operation will be slower.
Q10. If the length of a transistor increases, the current ____ and its gate capacitance _____.
a) Increases and Increases
b) Decreases and Increases
c) Increases and Decreases
d) Decreases and Decreases
Q11. In the Linear region, Ids depends on
a) Charge in the channel
b) How fast is the charge moving
c) Both a and b
d) None of the above
Q12. In layout designing, Feature Size F represents?
a) The distance between Gate and Source, set by minimum width of Polysilicon
b) The distance between Source and Drain, set by minimum width of Polysilicon
c) The distance between Gate and Drain, set by minimum width of Polysilicon
d) None of the above
Q13. How many transistors are required to design the following equation: Y = SD1 + SD0?
a) 15
b) 10
c) 25
d) 20
Q14. If the supply voltage of a chip increases, the maximum transistor current.
a) Increases
b) Decrease
c) Does not change
d) Causes an exponential decay
Q15. When Kn>kp, threshold voltage moves closer to.
a) Zero
b) Infinity
c) midpoint value
d) supply voltage
Answers: 1.c 2.d 3.a 4.a 5.d 6.c 7.a 8.a 9.c 10.b 11.c 12.b 13.d 14.a 15.a
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