If you recall in our last post we discuss about the different sources of power dissipation in CMOS circuits.In this post we shall be starting some discussion on how we can actually control or reduce power dissipation by making some design changes, design modifications following some design rules, various such techniques are there we shall be discuss them one by one.
Techniques to Reduce Power
Various techniques exist, both device level and architectural level, that address the issue of reducing power consumption.We shall discuss several techniques for reducing dynamic power and static power.
Techniques to reduce dynamic power:
Pdynamic = αCV2DD f
Techniques to reduce dynamic power:
Pdynamic = αCV2DD f
where α is the activity factor, C is the load capacitance, and f is the clock frequency.
Reduce α (clock gating, sleep mode)
Reduce C (small transistors, short wires)
Reduce VDD (reduce supply voltage such that the circuit operates correctly)
Reduce f (reduce clock frequency to the extent possible; power down mode)
Clock Gating
The clock gating technique which is one way to reduce alpha(α).
Basic idea of clock gating:
1.Clock is mainly responsible for the signal activities.
2.Switch off clock signal from the functional modules that are inactive.
3.Use additional hardware for the purpose.
4.Clock signal might get delayed due to increase in the critical path.
Power dissipation in a circuit is very much dependent on the signal transition activity or alpha(α).Clock is mainly responsible for signal activities.Clock is a signal which works like a brain of the entire system so when the clock transitions take place all the circuit elements work in synchronously. Sometimes we have not required that clock to some functional blocks if we disable this clock to that particular functional block then switching activity reduced and activity factor α is also reduce and power dissipation is also reduced.
We have a register where the input is loaded from there it is fed to functional unit, and the register is loaded by a clock not directly but loaded through the OR gate using disable signal.When we know we don’t require a functional unit we will set the disable to 1 so that the output of OR gate will be a constant one, the value of register will not change and therefore there will be no signal transition in the functional unit.When we are switching off the clock signal from the functional unit additional logic is required depending on the scenario that the functional unit required or not. But clock signal might add some delay in the critical path due to additional circuitry then skew analysis is required.
Possible strategy for managing skew:The OR gate can replace a buffer in the clock distribution tree.
Supply Voltage(Vdd) Reduction
We explore two design approach:
Static Approach: where the distribution of power supply voltages is fixed a priori among various functional blocks.
Dynamic Approach: where the power supply voltages is changed as required.
Voltage Reduction Static Approach
We analyze the circuit and we can reduce the supply voltage that will make circuit consumes less power but the circuit becomes may be slower so we have to analyze the circuit and find out which part of the circuit is not critical in terms of delay, we can possibly make that part little slower without touching the overall performances. So identify those parts and reduce the power supply for that.
Suppose we have a circuit having three functional modules let us assume we required the central block to be running fast but the other two blocks are running slower. So we use pair of voltage rails one is for low supply voltage and the other is for high supply voltage so the block which is supposed to run faster they are fed by the high supply voltage and the other two feed by low supply voltages, so voltage is saved.
The distribution of the voltage is always fixed.Additional power delivery network is required power routing becomes more complex.
Needs special care for interface between power domains.
Voltage Reduction Dynamic Approach
We are adjusting operating voltage and frequency not only voltage also frequency both we can adjust dynamically to match the performance requirement.Modern day processor can have several power modes.
1.High performance mode: High Vdd and f.
2.Power saving mode: Low Vdd and f.
This approach provides flexibility and does not limit performance.Penalty of transition between power states can be high it will take some time from one mode to another mode so it should not be done frequently. Additional control logic is required.
Voltage Islands (Multi‐VDD)
Now we see that how this multiple voltage is actually be implanted on a chip.Cells are arranged in a row, there are two different voltage domains high and low. All the cells which are supposed to high performance will be placed in high voltage domain and lower performance cells are placed in the low voltage domain.Orange and blue color indicate two different voltage levels ,orange indicate Vdd high and blue indicate Vdd low.
It allow both macro and cell voltage assignment.
Allow different voltage islands in the same circuit row but if we are doing this the problem of power routing will become more difficult if we mix them together.
Reducing Static Power
A combination of various techniques can be used:
1. Selectively use rationed circuits.
2. Selectively use low threshold NMOS and PMOS devices.
3. Use suitable leakage reduction techniques.
3. Use suitable leakage reduction techniques.
Static power reduction techniques
1.Power Gating
2.Variable Threshold Voltages
3.Multiple Threshold Voltages
Variable Threshold Voltages
We adjust the threshold voltages of the transistors at run‐ time to meet performance and power requirements.
Reducing Vth increases the sub‐threshold leakage current exponentially.
Reducing Vth also decreases the gate delay.
How to change threshold voltage?
By changing the body‐bias voltage.
For NMOS, the substrate is normally tied to ground (VSB = 0).
A negative bias on VSB causes VT to increase.
Adjusting the substrate bias at run-time is called adaptive body‐biasing (ABB) or dynamic threshold scaling (DTS).But only problem here is that if we want to have this kind of a facility fabrication becomes more complex because traditional CMOS fabrication requires a double well fabrication process,now we need a triple well fabrication process which increases the cost of fabrication.
Power Gating
Power gating is one of the techniques to reduce static power consumption. To reduce static current during sleep mode is to turn off the power supply to the sleeping blocks.
We can gate the supply rails when the circuit is in sleep mode.
In normal mode, sleep = 0 and the sleep transistors must present as small a resistance as possible (via sizing).
In sleep mode, sleep = 1 and the transistor stack effect reduces leakage by orders of magnitude.
We see normally we have this Vdd and Vss these two power supply voltages that is driving the gates. Now we have been auxiliary voltage at a lower level V DDV and V SSV. So, what we are saying is that sometimes we can set this circuit to the sleep mode by activating these transistors by setting this Sleep to 1.
So, if we said Sleep to 1 these transistors will be turned off. So, now, this circuit will be powered by this lower voltage. So, it is like power down mode. So, if we can put circuits to sleep, where we are not doing any computation right now, power consumption can be significantly reduced. Now see some of the circuits can also be storage elements flip flops. So, we really cannot switch off Vdd. So, if we switch off Vdd, your data stored in the memory elements might get lost. So, it is better to have a power down mode where we just reduce the voltage level, let the data storage be retained, but whenever else we required again we again jack of the voltage and start using it.
Power gating was originally proposed as multiple threshold CMOS (MTCMOS) because it used low-Vt transistors for logic and high-Vt for header and footer switch. Power gating can be done externally with disable input to a voltage regulator or internally with high-Vt header and footer switches. On-chip power gating can use a PMOS header switch transistor or NMOS footer switch transistors. NMOS transistors deliver more current per unit width so they can be smaller.
Power gating types:
1. Fine grained power gating: It is applied to individual logic gates, but placing this in every cell has enormous area overhead.
2. Coarse grained power gating: In this the switch is shared across an entire block.
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