1.Which of the following statements are correct related to the false path?
a)False path are exceptions applied to a timing path.
b)Change in source register are not making any changes in destination registers in a particular time interval that path is considered as false timing path.
c)False timing path has a start point and end point.
d)Change in source register making false or incorrect change in destination register in a particular time interval that path is considered as false timing path.
2.In a design there are 100 thousands flip flops and two external clocks signals present.If the design uses one 2:1 multiplexer for multiplexing clock signals, the maximum number of clock timing paths are.
a)one thousand
b)100 thousand
c)200 thousand
d)0
3.Which of the following is considered as a false timing path?
a)M1/1->M2/0
b)M1/1->M2/1
c)No false path is present
4.How many clock timing paths are present in the following circuits?
a)1
b)2
c)0
d)None of the above
5.How many capture flip flops are present in the below circuits?
a)1
b)2
c)3
d)4
6.How many launch flip flops are present in the below circuits?
a)0
b)1
c)3
d)4
7.How many data timing path are present in the below circuits?
a)1
b)2
c)3
d)4
8.If clock frequency is 4ns what are different possible clock edges (Launch flip flop clock edge,Capture flip flop clock edge) for setup check for below circuit?
a)0ns, 2ns
b)0ns, 4ns
c)0ns, 8ns
d)4ns, 0ns
9.What is maximum and minimum delay between FF1 and FF3?
Delay of all BUF =1.5ns and delay of IN5 =1ns and delay of AND1 =2.5ns and delay of AND2=3.5ns and delay of OR1=2.1ns and delay of NAND1=1.8ns.
a)11.4ns and 6.8ns
b)9.4ns and 6.8ns
c)11.4ns and 9.4ns
d)None of the above
10.How many setup reports can be reported by sta tool in the above circuit only for reg to reg path?
a)10
b)5
c)6
d)12
11.On which of the following factors does the maximum clock frequency depend?
11.On which of the following factors does the maximum clock frequency depend?
a)Gate delays
b)Interconnect delays
c)Clock skew
d).All of the above
12.For STA, which of the following statements is false?
12.For STA, which of the following statements is false?
a)A negative slack indicates that the RAT is greater than AAT.
b)A positive slack indicates that the AAT is greater than the RAT.
c)The slacks and AAT values are calculated first, from which the RAT values are calculated.
d)All of the above
13.A false path is a path in a combinational circuit in which
13.A false path is a path in a combinational circuit in which
a)The final output line for the path evaluates to 0 for all input combinations.
b)The path is never sensitized corresponding to any input combination.
c)The delay of the path is the longest.
d)A signal transition in the input can cause a data hazard in the output.
14.It is required to speed up the process of STA. Which of the following are typically used for the purpose?
14.It is required to speed up the process of STA. Which of the following are typically used for the purpose?
a)The circuit is modified such that no false paths exist.
b)The false paths are first identified and are excluded from the analysis.
c)The slack values are made zero by adjusting the delays.
d)None of the above
Answers: 1.a,b and c 2.c 3.a 4.b 5.c 6.c 7.d 8.b and c 9.a 10.d 11.d 12.d 13.b 14.b
Click here for part 3
https://www.vlsi4freshers.com/2020/06/sta-interview-questions-part-3.html
Click here for part 3
https://www.vlsi4freshers.com/2020/06/sta-interview-questions-part-3.html
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