Verilog Interview Questions Part 3

1. What logic is inferred when there are multiple assign statements targeting the same wire? It is illegal to specify multiple assign sta...

Verilog Code Examples

1.Write verilog code for implementation of 8*1 MUX using ASSIGN statement. Code: module mux_q1(output Y,input [7:0]In,[2:0]S); assign...

Verilog Interview Questions Part 2

1.If a net has no driver, it gets the value. a)0 b)X c)Z d)None of the above 2.Which logic level is not supported by verilog? ...

Verilog Interview Questions Part 1

Q1. Write a Verilog code using behavioral modeling for a 4-bit shift register? Q2. Write a Verilog code for positive edge triggered D-fli...