1. The base of the number system for the addition operation 24 +14=41 to be true is
(a) 8
(b) 7
(c) 6
(d) 5
2. The decimal equivalent of hexadecimal number of '2ADF is
(a) 17670
(b) 17607
(c) 17007
(d) 10767
3. Addition of all gray code to convert decimal (0-9) into gray code is
(a) 129
(b) 108
(c) 60
(d) 53
4. Consider X=(54)b, where 'b' is the base of the number system. If √X=7 then base 'b' will be
(a) 7
(b) 8
(c) 9
(d) 10
5. X=01110 and Y=11001 are two 5-bit binary numbers represented in two's compliment format. The sum of X and Y represented in two's compliment format using 6 bits is
(a) 100111
(b) 001000
(c) 000111
(d) 101001
6. A logic circuit implements the Boolean function F=X'.Y+X Y'.Z'. It is found that the input combination X=Y=1 can never occur. Taking this into account, a simplified expression for F is given by
(a) X'+Y'.Z'
(b) X+Z
(c) X-Z
(d) Y+X.Z'
7. When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero?
(a) Sign magnitude
(b) 1's complement
(c) 2S complement
(d) 9's complement
8. A signed integer has been stored in a byte using 2's complement format. We wish to store the same integer in 16-bit word. We should copy the original byte to the less significant byte of the word and fill the more significant byte with
(a) 0
(b) 1
(c) to equal to the MSB of the original byte
(d) complement of the MSS of the original byte
9. The sign-magnitude form and 2's complement form of a signed binary number (10111)2, are:
(a) -23 and -25
(b) -23 and -9
(c) -7 and -23
(d) -7 and -9
10. From the 7 symbols (0-6), how many different codes we can construct?
(a) 8!
(b) 8
(c) 7!
(d) 7
11. The number of digit '1' present in the binary representation of the number (1199)12
(a) 7
(b) 8
(c) 10
(d) 12
12. Which one of the following statements is correct? For a 4-input NOR gate, when only two inputs are to be used, the best option for the unused input is to
(a) Connect them to the ground
(b) Connect them to Vcc
(c) Keep them open
(d) Connect them to the used inputs
13. Assuming that only the X and Y logic inputs are available and their complements X' and Y' are not available, what is the minimum number of two input NAND gates required to implement X⊕Y?
(a) 2
(b) 3
(c) 4
(d) 5
14. A gate is disabled when its disable input 's at logic 0. The gate is
(a) OR
(b) AND
(c) NOR
(d) EX-OR
15. Consider a 4-input NAND gate, how many number of input conditions are possible, that will produce output "HIGH".
(a) 0
(b) 1
(c) 2
16. Consider the following statements:
A 4:16 decoder can be constructed (with enable Input) by:
1. using four 2:4 decoders (each with an enable input) only.
2. using five 2:4 decoders (each with an enable input) only.
3. using two 3:8 decoders (each with an enable input) only.
4. using two 3:8 decoders (each with an enable input) and an inverter.
Which of the statements given above is/are correct
(a) 2 and 3
(b) 1 only
(c) 2 and 4
(d) None of the above
17. The number of select lines required in a single input and '256' output DEMUX is
(a) 8
(b) 16
(c) 32
(d) 64
18. If carry propagation delay is 5Δ in full adder. then multiplication of 8 bit numbers using array co-multiplier takes (Assume AND gate delay = 2Δ)
(a) 72 Δ
(b) 74 Δ
(c) 70 Δ
(d) 82 Δ
19. The outputs Q and Q' of a master-slave flip-flop are connected to its R and S inputs respectively. Its output Q when clock pulses are applied will be
(a) fixed 0 or 1
(b) permanently 0
(c) permanently 1
(d) complementing with every clock pulse
20. The output Qn, of a J-K flip-flop is 1. It changes to 0 when a clock pulse is applied. The inputs J and K are respectively
(a) 0 and x
(b) 1 and x
(c) x and 0
(d) x and 1
21. A master-slave flip-flop is triggered
(a) when the clock input is at HIGH logic level
(b) when the clock input is at LOW logic level
(c) when the clock input makes a transition from LOW to HIGH
(d) when a pulse is applied at the clock input
22. For a flip-flop with provisions of preset and clear
(a) preset and clear operations are performed simultaneously.
(b) while clearing, preset is disabled.
(c) while presetting, clear is disabled.
(d) both (b) and (c) are correct.
23. Which of the following capabilities are available in a Universal Shift Register?
1. Shift left
2. Shift right
3. Parallel load
4. Serial add
Select the correct answer from the codes given below:
(a) 2 and 4 only
(b) 1, 2 and 3
(c) 1, 2 and 4
(d) 1, 3 and 4
24. A SISO shift registers may be used to introduce time delay Δt = 200 ns in digital signals. Assume this shift registers is manufactured by 'N' number of D-flip-flops having clock frequency 50 MHz . The required value of 'N' is
(a) 10
(b) 100
(c) 9
(d) 5
25. Data can be changed from spatial code to temporal code and vice versa by using
(a) ADCs and DACs
(b) Shift registers
(c) Synchronous counter
(d) Timers
26. A universal register
(a) accepts serial input
(b) accepts parallel input
(c) gives serial and parallel outputs
(d) is capable of all of the above
27. The 14-bit timer is loaded with the counter value of 07D0 H. The timer input is connected to a clock with a frequency of 800 KHz. The timer is programmed to produce a continuous signature wave output. The frequency of the square wave output is
(a) 400 kHz
(b) 800 kHz
(c) 400 Hz
(d) 2000 kHz
28. 12 MHz clock frequency is applied to a cascaded counter of modulus-3 counter, modulus-4 counter and modulus-5 counter. What are the lowest output frequency and the overall modulus, respectively?
(a) 200 kHz, 60
(c) 3 MHz, 12
(b) 1 MHz, 60
(d) 4 MHz, 12
29. The initial state of a Mod-20 counter is 10101. Counter design is in such a way that output of the logic gate (AND) is connected with preset of all the 5 FFs and FFs are triggered with (-)ve edge and clock connection is with complement of the FF output (Q). After 44 clock pulses, the state of the counter will be
(a) 11001
(b) 10010
(c) 11000
(d) 10001
30. A certain J-K-FF has propagation delay(tpd) = 12 ns. The largest Mod counter that can be designed from these FFs which still operate up to 10 MHz will be
(a) 8
(b) 9
(c) 10
(d) 256
Answers:
1. b 2. d 3.d 4.c 5.c 6.d 7.c 8.c 9.d 10.a 11.a 12.a 13.d 14.b 15.d 16.c 17.a 18.a 19.d 20.d 21.d 22.d 23.b 24.a 25.b 26.d 27.c 28.a 29.d 30.d
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