# Texas Instruments Digital Design Profile Interview Questions

1. Read the given statements S1 and S2 carefully and choose the appropriate option.
S1: DRAM storage cells can retain their state even after they are powered off and the rate of decay of charge decreases with decrease in temperature.
S2: The leakage current doubles for every 100 C increase in temperature.
a) S1 is correct. S2 is correct. S2 is the correct explanation of S1.
b) S1 is correct. S2 is correct. S2 is not the correct explanation of S1.
c) S1 is correct. S2 is incorrect.
d) S1 is incorrect. S2 is correct.
2. You are given a Final State Machine(FSM) with N states. You now want to encode the states either using the Grey Encoding Scheme or the One Hot Encoding Scheme.

What should be the maximum value of N so that the number of Flip Flops in the sequential circuit obtained from the FSM is lesser for the One Hot encoded scheme?

a) 2
b) 3
c) 4
d) This is not possible to achieve.
3. A new type of keyboard is being developed with the same functionality as a regular QWERTY keyboard. However, the newly developed will have reduced number of keys. Given below are some key combinations that will map to a character in this keyboard:

K1 + K4 + K6 = A

K2 + K5 + K3 = B

K2 + K5 = C

K2 = D

Which of these digital circuit elements can be used to implement this keyboard ?

a) Multiplexer

b) Demultiplexer

c) Priority Encoder

d) Decoder

4. You have three delay elements D1, D2, D3 that delay a clock by 25%, 50% and 75% respectively.
Which of the following options correctly mentions the desired elements to design a frequency doubling(fout = 2*fip) circuit?

a) One D1 and Two XOR

b) One D1 and One XOR

c) One D2 and Two XOR

d) One D3 and One XOR

5. It is given that the word line of a DRAM is asserted causing the pass transistor to open up. You notice that this leads to dissipation of charge over the digit line causing voltage change in the capacitor.

In the given context, which of these parameters will affect the final charge on the capacitor ?

1. Capacitance of the word line

2. Capacitance of the DRAM cell capacitor

3. Capacitance of the digit line

a) 1,2

b) 1,3

c) 2,3

d) 1,2,3

6. You want to write a program that counts the number of 0’s in a certain register. Which of these operations will be required to do this ?

1. JNZ

2. JC

3. JNC

a) Only 1

b) Only 1 and 2

c) Only 2 and 3

d) None of these

7. You are running the following instruction on a 8085 board.

MVI C, 23H

It is given that you punch in the opcode DE followed by 23 in hexadecimal. Which bit(s) of the opcode(representation in binary) starting from LSB should you flip in the order to ensure that the data is stored in the register E and not in C?

a) 2nd bit

b) 6th bit

c) 9th bit

d) 8th bit

8. The following function needs to be implemented using only a 2:1 MUX cell.

DA (A, B, x) = (1,3,5,6)

DB (A, B, x) = (2,3,4,5)

What is the minimum number of MUX cells needed to do this ?

Notes:

• All states should be triggered by positive edge of the clock.

• DA, DB are next states. A, B are present states.

• x is the input and Y is the output.

• RHS represents min terms.

a) 8

b) 10

c) 14

d) 18

9. Analyse the following verilog code and determine the variable that will be assigned last and the timestamp for the same.
Initial
fork
a = 0;
#20 b = 0;
#40 c = 0;
#30 d = 0;
join
Note: Assume that the execution of the initial block begins at time  = 0ns.The timestamp is 1ns/1ps
a) Variable - d
Timestamp - 90ns
b) Variable - c
Timestamp - 40ns
c) Variable - c
Timestamp - 90ns
d) None of these
10. You are given two flips flops FF1 and FF2. As shown in figure, FF2 is a modified version of FF1.
If the setup times of FF1 is Tsetup and the delay of the internal buffer is Tbuf, what is the setup time Tsetup_ff2 of FF2?
a) Tsetup_ff2 = Tsetup + Tbuf
b) Tsetup_ff2 = Tsetup - Tbuf
c) Tsetup_ff2 = Tsetup / Tbuf
d) None of these
11. You want to build the following counters and also build decoder circuits for the same.
1. Twisted Ring counter
2. Standard Ring counter
3. Binary counter
It is given that NF is the number of Flip Flops needed to design the counter and CD is the complexity of the decoding circuit. You want to rank the above counters based on the deceasing order of NF and CD.
In the given context, which of these choices correctly represents the ranking orders?
a) NF: 2>1>3
CD: 3>1>2
b) NF: 3>1>2
CD: 2>1>3
c) NF: 1>2>3
CD: 3>2>1
d) NF: 2>1>3
CD: 1>3>2
12. You are given a 2:1 MUX and an INVERTER as a basic cell to implement certain function.
In the given context, what is the minimum number of basics cell required to implement nine variable functions?
a) 16
b) 18
c) 20
d) 21
13. You want to create a SR latch like structure from the given code snippet for a 4x1 MUX.
Case ({ v_1, v_0 })
00: out = inp0;
01: out = inp1;
10: out = inp2;
11: out = inp3;
default: out = inp2;
endcase
You can do this by removing any lines from the code snippet. However, you cannot add any lines. What is the minimum number of lines that should be removes to achieve your objective?
Note: Assume that the variables have been declared and the code has been defined.
a) 1
b) 2
c) 3
d) 4
14. You are working on a system of chip (SOC) as shown in the figure given below. When signing off
you find a glitch generated at one very specific location in the design where clock net and data net (constantly driven at logic 0) are very close to each other. On further analysis you find that this is not a flaw in the design (RTL code).
Which of these improvements in the design will not be helpful in minimizing the glitch effect?
Note:
Cc is coupling capacitance between clock net and data net
Cg is the grounded capacitance of data net
CL is the load at the fanout cell F2.
a) Increase Cg
b) Decrease CL
c) Decrease Cc
d) Decrease the drive strength of CELL 1
15. You are given a circuit wherein the input is divided into the following two channels.
1. The first channel goes into one of the inputs of the XOR gates.

2. The second channel goes into the input of the XOR gate but after passing through  N inverters.

You are expecting this circuit to generate an output wave of time period T/2 with 50% Duty cycle. What should the value of X be in terms of T so that the desired output is obtained ?

Notes:

The propagation delay of the inverters I1, I2, I3 …In can be given as X, X/2, X/4…X/(2^(n-1)).

The Time Period of the input clock is T with the 50% Duty Cycle.

N is a very large even number.

a)T/4

b) T/8

c) T/2

d) T/16

16. You need to implement the Logic shown in the given figure with the below specifications:

1. PinA = S0 when input is an even number

2. PinB = S1 when input is an odd number

How many 4:1 Mux and 2:4 Demux will you require to design the Logic?

a) 4:1 Mux - 1

2:4 Demux - 2

b) 4:1 Mux - 1

2:4 Demux - 1

c) 4:1 Mux - 2

2:4 Demux - 2

d) 4:1 Mux - 0
2:4 Demux - 2

17. You have designed a system having the following state diagram. It is given that system is initially in state Sa.

Which of these choices best describes the sequence of state that the system could have gone through if it is finally in state Sc?

Note: * represent zero or more occurrence of a logic level and + represents one or more

occurrence of a logic level.
a) 0*->1+->0+
b) 0*->1*->0*
c) 0*->0*->1
d) 0+->1+->0*
18. A set of n inputs (n>2) is passed to a series of XNOR gates connected in a cascaded manner as shown. which of these choices correctly represent the boolean expression for OUT?
a) a1 xor a2 xor a3___xor an.
b) a1 xnor a2 xnor a3___xnor an.
c) a1 xor a2 xor a3___xor an if n is even
a1 xnor a2 xnor a3___xnor an if n is odd
d) a1 xor a2 xor a3___xor an if n is odd
a1 xnor a2 xnor a3___xnor an if n is even
19. You are given the following binary decision diagram (BDD) containing nodes followed by solid or broken lines. It is given that the nodes are input variables and the solid lines are high child and the broken lines are low child.
For instance if we follow solid lines on the extreme left , it results in a.b.c.d=0 and if we follow set of broken lines on the extreme right , it results in a'.b'.c'.d'=0.
Analyze the BDD and find which of these expressions correctly represents it.
a) (a.b).(c+d)
b) (a xnor b) . (c xnor d)
c) (ab'+a'b').(cd'+c'd')
d) (a xor b) . (c xor d)
20. It is given that the following digital circuit is prone to hazards
Which of the following statements are valid in the given scenario?
1. The hazard is observed when two signals that occur at different intervals try to cancel each other.
2. The hazard is observed at G1 and propagated from G2 to the final output G3
3. The hazard can propagate through G3 only when Z is high.
a) 1,2
b) 1,3
c) 2,3
d) 1,2,3

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